zl30102 Zarlink Semiconductor, zl30102 Datasheet - Page 20

• Manufacturer Part Number: zl30102
• Description: T1/e1 Stratum 4/4e Redundant System Clock Synchronizer For Ds1/e1 And H.110
• Manufacturer: Zarlink Semiconductor

4.4
The ZL30102 has three possible manual modes of operation; Normal, Holdover and Freerun. These modes are
selected with mode select pins MODE_SEL1 and MODE_SEL0 as is shown in Table 4. Transitioning from one
mode to the other is controlled by an external controller. The ZL30102 can be configured to automatically select a
valid input reference under control of its internal state machine by setting MODE_SEL1:0 = 11. In this mode of
operation, a state machine controls selection of references (REF0 or REF1) used for synchronization.
4.4.1
Freerun mode is typically used when an independent clock source is required, or immediately following system
power-up before network synchronization is achieved.
In Freerun mode, the ZL30102 provides timing and synchronization signals which are based on the master clock
frequency (supplied to OSCi pin) only, and are not synchronized to the reference input signals.
The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a
is required, the master clock must also be
4.4.2
Holdover Mode is typically used for short durations while network synchronization is temporarily disrupted.
In Holdover Mode, the ZL30102 provides timing and synchronization signals, which are not locked to an external
reference signal, but are based on storage techniques. The storage value is determined while the device is in
Normal Mode and locked to an external reference signal.
When in Normal Mode, and locked to the input reference signal, a numerical value corresponding to the ZL30102
output reference frequency is stored alternately in two memory locations every 26 ms. When the device is switched
into Holdover Mode, the value in memory from between 26 ms and 52 ms is used to set the output frequency of the
device. The frequency accuracy of Holdover Mode is 0.1 ppm.
Two factors affect the accuracy of Holdover mode. One is drift on the master clock while in Holdover mode, drift on
the master clock directly affects the Holdover mode accuracy. Note that the absolute master clock (OSCi) accuracy
does not affect Holdover accuracy, only the change in OSCi accuracy while in Holdover. For example, a
master clock may have a temperature coefficient of
ZL30102 is in Holdover mode may result in an additional offset (over the 0.1 ppm) in frequency accuracy of
±
jitter on the reference input prior to the mode switch.
1 ppm. Which is much greater than the 0.1 ppm of the ZL30102. The other factor affecting the accuracy is large
Modes of Operation
Freerun Mode
Holdover Mode
MODE_SEL1
0
0
1
1
MODE_SEL0
0
1
0
1
±
Table 4 - Operating Modes
32 ppm. See Applications - Section 6.2, “Master Clock“.
Zarlink Semiconductor Inc.
ZL30102
±
0.1 ppm per °C. So a
20
(Normal with automatic Holdover and
Normal (with automatic Holdover)
automatic reference switching)
Automatic
Holdover
Freerun
Mode
±
10 °C change in temperature, while the
±
32 ppm output clock
Data Sheet
±
32 ppm