zl30102 Zarlink Semiconductor, zl30102 Datasheet - Page 19

• Manufacturer Part Number: zl30102
• Description: T1/e1 Stratum 4/4e Redundant System Clock Synchronizer For Ds1/e1 And H.110
• Manufacturer: Zarlink Semiconductor

4.0
4.1
The out of range limits for the Precise Frequency Monitor in the 3 reference monitor blocks are selected through the
OOR_SEL pin, see Table 1.
4.2
The loop filter and limiter settings are selected through the SEC_MSTR pin, see Table 2. The maximum loop filter
bandwidth is also dependent on the frequency of the currently selected reference (REF0/1/2).
4.3
The output of the DCO is used by the frequency synthesizers to generate the output clocks and frame pulses which
are synchronized to one of three reference inputs (REF0, REF1 or REF2). These signals are available in two
groups controlled by the OUT_SEL pin, see Table 3.
Out of Range Selection
Loop Filter and Limiter Selection
SEC_MSTR
Output Clock and Frame Pulse Selection
Control and Modes of Operation
OOR_SEL
0
1
0
1
OUT_SEL
0
1
Detected REF Frequency
8.192 MHz, 16.384 MHz
1.544 MHz, 2.048 MHz,
Table 3 - Clock and Frame Pulse Selection with OUT_SEL Pin
Application
DS1
E1
8 kHz
any
Table 2 - Loop Filter and Limiter Settings
Table 1 - Out of Range Limits Selection
C2o, C16o, C32, C65o
C2o, C4o, C8o, C16o
Generated Clocks
Telcordia GR-1244-CORE Stratum 4/4E
Zarlink Semiconductor Inc.
ZL30102
Applicable Standard
Loop Filter Bandwidth
ETSI ETS 300 011
19
ANSI T1.403
ITU-T G.703
922 Hz
1.8 Hz
58 Hz
Generated Frame Pulses
F16o, F32o, F65o
F4o, F8o, F16o
Phase Slope Limiting
Out Of Range Limits
9.5 ms /s
9.5 ms /s
100 - 130 ppm
61 µ/s
64 - 83 ppm
Data Sheet