fms9884akac175 Fairchild Semiconductor, fms9884akac175 Datasheet - Page 5

• Manufacturer Part Number: fms9884akac175
• Description: 3x8-bit, 108/140/175 Ms/s Triple Video A/d Converter With Clamps
• Manufacturer: Fairchild Semiconductor

FMS9884A
Pin Descriptions
REV. 1.2.2 12/7/01
Converter Channels
Timing Generator
Phase Locked Loop
Sync Stripper
Control
R
Pin Name
IN
INVSCK
DCS
PWRDN
CLAMP
HSOUT
DGA
DGB
COAST
DRA
DRB
DBA
DBB
ACS
, G
HSIN
DCK
DCK
XCK
SDA
SCL
LPF
A
A
IN
0
1
OUT
7-0
7-0
7-0
7-0
7-0
7-0
IN
, B
IN
7, 15, 22
105–112
Pin No.
95–102
85–92
75–82
65–72
55–62
115
116
117
118
125
28
27
44
40
41
45
14
29
30
31
32
Bi-directional Serial Port Data. Bi-directional data.
Type/Value
Passive
Schmitt
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Pin Function Description
Analog Inputs.
Red Channel Port A Data Output. Full rate/half rate, interleaved/
parallel data depending upon selected mode.
Red Channel Port B Data Output. Active for dual port mode only with
interleaved/parallel outputs. High impedance when inactive.
Green Channel Port A Data Output. See red channel port A.
Green Channel Port B Data Output. See red channel port B.
Blue Channel Port A Data Output. See red channel port A.
Blue Channel Port B Data Output. See red channel port B.
External Clamp Input.
Invert Sampling Clock. Inverts SCK, the internal clock sampling the
analog inputs. Supports Alternate Pixel Sampling mode for capture
pixel rates up to 350Ms/s.
External Clock input. Enabled if register bit, XCKSEL = H. Replaces
PXCK clock generated by PLL. If unused, connect to ground through a
10kΩ resistor.
Output Data Clock. Clock for strobing output data to external logic.
Output Data Clock Inverted. Inverted clock for strobing output data to
external logic.
Horizontal Sync Output. Reconstructed HSYNC delayed by
FMS9884A latency and synchronized with DCK. Leading edge is
synchronized to start of data output. Polarity is always active HIGH.
Horizontal Sync input. Schmitt trigger threshold is 1.5V. A 5V source
should be clamped at 3.3V or current limited to prevent overdriving
ESD protection diodes.
PLL Coast. Maintain frequency of PLL output clock PXCK,
disregarding HSIN. If horizontal sync is missing during the vertical sync
interval, PXCK clock frequency can be maintained by asserting
COAST.
PLL Low Pass Filter. Connect recommended PLL filter to LPF pin.
(see Figure 19.)
Analog Composite Sync Input. Input to sync stripper with 150mV
threshold.
Digital Composite Sync Output. Output from sync stripper.
Serial Port Clock. Clock input.
Address bit 0. Lower bit of serial port address.
Address bit 1. Upper bit of serial port address.
Power Down/Output Control. Powers down the FMS9884A and
tri-states the outputs.
PRODUCT SPECIFICATION
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