ml87v2104 Oki Semiconductor, ml87v2104 Datasheet - Page 8

• Manufacturer Part Number: ml87v2104
• Description: Display Controller With Built-in Display Memory And Jpeg
• Manufacturer: Oki Semiconductor

PEDL87V3116-02
OKI Semiconductor
ML87V3116
FUNCTIONAL DESCRIPTION
1. General Description
The ML87V3116 is comprised of the following blocks.
1.1 Video Input Interface
The video input interface has two video input ports, and stores image data input from either port into the Data
Buffer.
1.2 Display Interface
The display interface outputs image data written into the Data Buffer to the external display unit.
Either color TFT-LCD or TV format can be selected as an output format.
1.3 JPEG Codec
JPEG Codec compresses image data using the JPEG method or decompresses a JPEG file into image data
Furthermore, JPEG Codec can perform a Motion-JPEG operation by repeating the above. JPEG Codec manages
the address of each frame using an index during a Motion-JPEG operation.
As the storage location of image data and JPEG files, both internal and external Data Buffers can be selected.
1.4 Rectangle Copy Controller
The rectangle copy controller copies the data in the specified rectangle area into another rectangle area within the
Data Buffer. It can reduce the size or rotate images when copying them.
1.5 Data Buffer + Data Buffer Controller
This memory buffer stores video input data, display data and other image data. It is virtually handled as
two-dimensional 16-bit deep memory.
This memory supports images with more pixels than the memory capacity by varying the aspect ratio.
Furthermore, external memory can be added as an address extension of this memory. By storing multiple JPEG
files into an extension data buffer during a Motion-JPEG operation, for instance, the moving picture
recoding/playback time can be extended.
1.6 Host Interface
The host interface allows access to the control register of each block and two memory buffers, including external
memory. A type of an interface that is compatible with various CPU buses can be selected by mode pin
(HMOD3-0) setting.
1.7 Clock/Power Manager
The clock/power manager controls the generation and stopping of the operating clocks of each block.
8/47