ml87v2104 Oki Semiconductor, ml87v2104 Datasheet
ml87v2104
Related parts for ml87v2104
ml87v2104 Summary of contents
Page 1
... OKI Semiconductor ML87V3116 Display Controller with Built-in Display Memory and JPEG GENERAL DESCRIPTION The ML87V3116 is a multi-function image processor LSI for small imaging devices. Imaging functions, such as image input, temporary storage, processing and display output, are integrated into a single chip. The ML87V3116 has functions includuing camera or video input image capture, display control in LCD or TV format, compression and decompression of still pictures and moving pictures (Motion-JPEG) using a JPEG engine, and image copying with the size reduction and the rotation ...
Page 2
... OKI Semiconductor BLOCK DIAGRAM YCbCr 8/16 Camera/ 16 Video input video interface input Camera master control Host interface 8/16-bit CPU bus External Data buffer SDRAM (1 Mbytes) D16 D64 16 Data buffer controller Rectangle JPEG copy Codec controller Clock/power Memory stick manager controller SD/MMC or ...
Page 3
... OKI Semiconductor PIN CONFIGURATION (TOP VIEW) 132 133 176 1 Index mark (top side) 176-Pin Plastic LQFP PEDL87V3116-02 ML87V3116 3/47 ...
Page 4
... OKI Semiconductor PIN DESCRIPTIONS Table-P1 Pin List (1/7): Video Input Related Pin No. Symbol 139-144, 146, 147 VY7-0 148-151, 153-156 VC7-0 159 VHS 158 VVS 161 VFID 160 VCLK Table-P2 Pin List (2/7): Display Output Related Pin No. Symbol 78, 77, 75-72 DG7-2 71 DG1LDP2 70 DG0LDP3 68-65, 63, 62 DB7-2 ...
Page 5
... OKI Semiconductor Table-P3 Pin List (3/7): SDRAM Interface Related Pin Symbol 137-134, 131-128, MDQ15-00 118, 119, 121-126 104, 102-97, MA12-00 95-90 106,105 MBA1-0 109 MWEN 111 MDQM 107 MRASN 108 MCASN 115-117 MCSN1-3 112 MCKE 113 MCLK Table-P4 Pin List (4/7): Host Interface Related ...
Page 6
... OKI Semiconductor Table-P5 Pin List (5/7): Peripheral Interface Related Pin Symbol 164 SDA 163 SCL 50 SSDO 49 SSDIO 48 SSCK 47 SSCE 29 SDCD3 30 SDCD2 31 SDCD1 32 SDMSCD0 33 SDMSCMD 34 SDMSCLK 36 SDMSDTN 37 SDWP 46 SDPWR Table-P6 Pin List (6/7): System Control Pin Symbol 42 REFCLK 27 RESETN 39-41 TMOD2-0 51 TOUT 38 SCAN I/O Type Input LVTTL ...
Page 7
... OKI Semiconductor Table-P7 Pin List (7/7): Power Supply Pin Symbol 35, 52, 76, 88, VDD1 103, 127, 138, 176 28, 45, 69, 81, VSS1 110, 132, 133, 169 8, 22, 64, 89, VDD2 114, 152, 162 1, 15, 58, 96, VSS2 120, 145, 157 44 VDDP 43 VSSP Description I/O power supply (3.3V) I/O ground Core power supply (2 ...
Page 8
... OKI Semiconductor FUNCTIONAL DESCRIPTION 1. General Description The ML87V3116 is comprised of the following blocks. 1.1 Video Input Interface The video input interface has two video input ports, and stores image data input from either port into the Data Buffer. 1.2 Display Interface The display interface outputs image data written into the Data Buffer to the external display unit. ...
Page 9
... OKI Semiconductor 2. Function of Each Block 2.1 Video Input Interface 2.1.1 Video Input Ports There are three types of video input formats. • BT.656 format : An 8-bit format defined in ITU-R Rec. BT.656 • 8-bit format : A format that deletes the synchronous reference code (EAV/SAV) from BT.656 format, ...
Page 10
... OKI Semiconductor 2.1.3 Input Image Format Specify the image area to be loaded into the data buffer for video input. Specify the start position and size of the effective image area for input synchronous signals using the control register. Furthermore, specify the position on the data buffer where that image area written using the address of the upper left origin ...
Page 11
... OKI Semiconductor [Control Registers] • VITRIG : Starts image capture/status, 1 bit (write/read write, starts image capture when “1” is written, and stops forcibly when “0” is written read, “1” indicates capturing, and “0” indicates the completion of capture. • VIMOD : Image capture mode, 1 bit (write/read) “ ...
Page 12
... OKI Semiconductor 2.2 Display Interface 2.2.1 Display Output Format The TFT-LCD mode or TV mode can be selected as a display output format. • TFT-LCD mode : Progressive scan, output synchronization, variable number of pixels • TV mode : Interlace scan, fixed to 525i or 625i [Control Registers] • DOFMT : Display format, 1 bit (write/read) “ ...
Page 13
... OKI Semiconductor • Data clock The polarity of CP can be selected. • LDP1-4 : Line drive pulse (4 types) The pulse cycle is common to LDP1-4, and the pulse width, pulse phase and pulse polarity can be specified in units of the number of CP clocks. When in the TV mode, LDP1 is automatically set and used as a HSYNC. ...
Page 14
... OKI Semiconductor [Control Registers] • CPPOL : Synchronous polarity selection for CP and output data, 1 bit (write/read) “0”: Synchronizes on the rising edge of CP, “1”: Synchronizes on the falling edge of CP • HLCYC : HST/LDP cycle (units of the number of CP clocks), 11 bits (write/read) • HST1POL : HST1 pulse polarity selection, 1 bit (write/read) “ ...
Page 15
... OKI Semiconductor • LDP2IO : Specify the LDP2 signal in GPIO6, 1 bit (write/read) "0": Synchronous signal, "1": GPIO (same for the following) • LDP3IO : Specify the LDP3 signal in GPIO5, 1 bit (write/read) • LDP4IO : Specify the LDP4 signal in GPIO4, 1 bit (write/read) • HST1IO : Specify the HST1 signal in GPIO3, 1 bit (write/read) • ...
Page 16
... OKI Semiconductor 2.2.3 Display Data Formats The RGB format or YCbCr format can be selected as a display data format. Because the data in a data buffer is in 16-bit YCbCr, 4:2:2 format, color space conversion is performed after expanding into 24-bit, 4:4:4 format first. Cb/Cr data is interpolated when expanding from 4:2:2 format to 4:4:4 format. ...
Page 17
... OKI Semiconductor 2.2.4 Display Data Area Partition, Display/Hide The effective data area of the display output can be divided into four partitions. Horizontal division or vertical division can be selected, and the data buffer address of data to be displayed in each of the four areas can be specified individually. Also, the specified area can be hidden. Hidden areas are not used to read the data buffers. ...
Page 18
... OKI Semiconductor Horizontal Partition Mode Area 0 Area 1 Area 2 Area 3 [ACTHED] - [ACTHST] Vertical Partition Mode Area 0 Area 1 Area 2 Area 3 [ACTHED] - [ACTHST] Figure 2.4 Display Area Partitioning PEDL87V3116-02 [DIVAP1] [DIVAP2] [DIVAP3] Display screen [DIVAP1] [DIVAP2] [DIVAP3] Display screen ML87V3116 18/47 ...
Page 19
... OKI Semiconductor Data buffer [DA1SAX] [DA3SAX] [DA1SAY] [DA3SAY] [DA0SAX] [DA0SAY] [DA2SAX] [DA2SAY] Figure 2.5 Display Address Specification (Example in Vertical Partition Mode) PEDL87V3116-02 ML87V3116 Display outputs Area 0 Area 1 Area 2 Area 3 19/47 ...
Page 20
... OKI Semiconductor 2.3 JPEG Codec 2.3.1 General Description JPEG Codec compresses and decompresses image data. When compressing images, JPEG Codec uses a rectangle area specified in the Data Buffer as the source image, sequentially reads data into block forms, compresses data using the JPEG method, and then converts the compressed data to a compressed data file in the JFIF format ...
Page 21
... OKI Semiconductor 2.3.3 Moving Picture Mode The size of a compressed data file in each frame is restricted by the segment size specification. For the segment size, any of 256/512/1K/2K/4K/8K/16K/32K/64K bytes can be selected according to the image size. (Be careful so that the compressed data file size does not exceed the segment size.) The addresses of compressed data files are managed using index pointers ...
Page 22
... OKI Semiconductor 2.4 Rectangle Copy Controller 2.4.1 General Description The rectangle copy controller reads data from the specified rectangle area (copy source), reduces and/or rotates it, and writes it into another specified area (copy destination). Specify the start addresses (X start, Y start) (upper left coordinates) of the copy source and copy destination and the rectangle size (X size, Y size), and perform a copy operation using a startup command ...
Page 23
... OKI Semiconductor 2.4.2 Specifying a Rectangle Area Specify a rectangle area using the start address (Xadrs, Yadrs) and size (Xsize, Ysize). For the start address, specify the start addresses using an upper left point of a rectangle area even when copying by rotating. Be sure to specify a rectangle area within the range of the buffer memory size in use. ...
Page 24
... OKI Semiconductor 2.4.3 Rotation Processing in Block The copy controller rotates the rectangle area specified by the host CPU, and copies it into an area of the copy destination. C data when rotating 90° or 270° is thinned out and its position is adjusted. <<Rotation angles>> Clockwise rotation: 0°, 90°, 180°, 270° ...
Page 25
... OKI Semiconductor 2.5 Data Buffer and Controller 2.5.1 General Description A data buffer is a memory buffer having two-dimensional addresses. The memory size is 1 Mbyte and the depth is 1 pixel (16 bits). Write/read access to the Data Buffer is always performed via block access. External SDRAM is called an extension Data Buffer, which is assumed as an address extension area of the internal Data Buffer ...
Page 26
... OKI Semiconductor Horizontal (511 pixels max.) (0,0) Vertical (1024 lines max.) Vertical (24703 lines max.) Vertical (4940 lines max.) Vertical (98815 lines max.) Vertical (197631 lines max.) Vertical Horizontal (1023 pixels max.) Horizontal (2047 pixels max.) Internal sdram External sdram Figure 2.5.1 Image of Buffer Memory Size ...
Page 27
... OKI Semiconductor Logical address 181FFFF 0020000 001FFFF 0000000 Figure 2.5.2 Data Buffer Memory Map Invalid bank Maximum (when configured with 512 Mbits x 3) Extension data buffer 3 Extension data buffer 2 Extension data buffer 1 Internal data buffer (8 Mbits) Y(max) Inv ...
Page 28
... OKI Semiconductor 2.6 Host Interface 2.6.1 General Description The host interface allows access to the control register of each block and the internal/external Data Buffers. A type of an interface that is compatible with various CPU buses can be selected by mode pin (HMOD3-0) setting. 2 Also, there are bus master and synchronous serial interface master that can directly be controlled by the host interface ...
Page 29
... OKI Semiconductor 2.6.2 Bus Control Signals The assignment of the bus control signals to the input/output pins is determined by the host interface bus mode. Pin name A0 A18-16 A18-16 AD15-00 A15-00 D07-00 D07-00 REGS REGS CSN CSN REN REN WEN WEN BSN — DSN — BSYN ...
Page 30
... OKI Semiconductor [Bus Interface Timing] (1) A0-Type Write BCLK CSN REGS A18-00 REG WEN (z) D7-0 (write) BSYN (2) A0-Type Read BCLK CSN REGS A18-00 REG REN (z) D7-0 (read) BSYN PEDL87V3116-02 ML87V3116 MEM MEM 30/47 ...
Page 31
... OKI Semiconductor (3) A1-Type Write BCLK CSN BS REGS A18-00 REG WEN (z) D7-0 (write) BSYN (4) A1-Type Read BCLK CSN BS REGS A18-00 REG REN (z) D7-0 (read) BSYN PEDL87V3116-02 ML87V3116 MEM MEM 31/47 ...
Page 32
... OKI Semiconductor (5) A2-Type Write BCLK CSN BSN REGS A18-00 REG WEN (z) D7-0 (write) ACK (6) A2-Type Read BCLK CSN BSN REGS A18-00 REG REN (z) D7-0 (read) ACK PEDL87V3116-02 ML87V3116 MEM MEM 32/47 ...
Page 33
... OKI Semiconductor (7) A4-Type Write BCLK CSN BSN REGS A18-00 REG RWN (z) D7-0 (write) ACK (8) A4-Type Read BCLK CSN BSN REGS A18-00 REG RWN (z) D7-0 (read) ACK PEDL87V3116-02 ML87V3116 MEM MEM 33/47 ...
Page 34
... OKI Semiconductor (9) A5-Type Write BCLK CSN BSN REGS A18-00 REG RWN (z) D7-0 (write) BSYN (10) A5-Type Read BCLK CSN BSN REGS A18-00 REG RWN (z) D7-0 (read) BSYN PEDL87V3116-02 ML87V3116 MEM MEM 34/47 ...
Page 35
... OKI Semiconductor (11) B0-Type Write BCLK CSN ASN REGS A18-16 WEHN WELN (z) AD15-0 A BSYN (12) B0-Type Read BCLK CSN ASN REGS A18-16 REN (z) AD15-0 A BSYN D (write (read) PEDL87V3116-02 ML87V3116 D (write) D (read) 35/47 ...
Page 36
... OKI Semiconductor (13) B1-Type Write BCLK CSN AS REGS A18-16 WEHN WELN (z) AD15-0 A BSYN (14) B1-Type Read BCLK CSN AS REGS A18-16 REN (z) AD15-0 A BSYN MEM D (write) A MEM D A (read) PEDL87V3116-02 ML87V3116 D (write) D (read) 36/47 ...
Page 37
... OKI Semiconductor 2.7 Clock/Power Manager 2.7.1 General Description The system clock of the ML87V3116 uses the same pixel clock frequency as display output or a frequency of x2 x8. This clock generates the REFCLK input by a built-in PLL using simple integer ratio n/m (n and m are 1 to 255 reference. Power saving can be achieved by setting to a slower system clock frequency at standby ...
Page 38
... OKI Semiconductor 2.7.2 Clock Generation The system clock of the ML87V3116 uses x2 the pixel clock frequency of display output. This clock generates the REFCLK input by a built-in PLL using simple integer ratio n/m (n and m are 1 to 255 • reference. (System clock = n/m The clock for JPEG is generated by the frequency divider of another system, and can be operated even at a slower speed than the system clock ...
Page 39
... OKI Semiconductor ABSOLUTE MAXIMUM RATINGS Parameter Symbol I/O power supply Core power supply PLL power supply VDDP Input voltage Output voltage Output short-circuit current Power dissipation Storage temperature RECOMMENDED OPERATING CONDITIONS Parameter Symbol I/O power supply Core power supply PLL power supply VDDP Operating temperature Note: Turn on the power in the order of VDD1, VDD2, and then VDDP ...
Page 40
... OKI Semiconductor ELECTRICAL CHARACTERISTICS DC Characteristics (VDD1 = 3.3 V ± 0.3 V, VDD2 = VDDP = 2.0 V ± 0.15 V, VSS = ° C) Parameter “H” level input voltage “L” level input voltage “H” level output voltage For SDRAM “L” level output voltage “H” level output voltage Others “ ...
Page 41
... OKI Semiconductor AC Characteristics (VDD1 = 3.3 V ± 0.3 V, VDD2 = VDDP = 2.0 V ± 0.15 V, VSS = ° C) Parameter Operating frequency (internal clock) BCLK clock period BCLK “H” level pulse width BCLK “L” level pulse width Input setup time ( → BCLK) Input hold time ( → BCLK) Output delay time (BCLK → ...
Page 42
... OKI Semiconductor TIMING DIAGRAMS (1) AC Characteristics tWH1 BCLK INPUT (CSN, BSN, DSN, WEN, REN, AD, D) OUTPUT (BSYN, INT, AD, D) REFCLK CP OUTPUT (DRn, DGn, DBn, LCP, FRP, DF) VCLK INPUT (VHS, VVS, VFID, VYn, VCn) tCK1 tWL1 tS1 tH1 tPD1 (a) Host Interface tCK2 ...
Page 43
... OKI Semiconductor (2) Color TFT, horizontal timing LDP CP DR7-0 n-2 n-1 DG7-0 n-2 n-1 DB7-0 n-2 n-1 (3) Color TFT, vertical timing FDPn TLCP LDPn DR7-0 DG7-0 DB7-0 TCP (ACTHED-ACTHST) [TCP] (HLCYC+1) [TCP] Line 0 Line 1 Line 2 Line 3 Line 0 Line 1 ...
Page 44
... OKI Semiconductor PACKAGE DIMENSIONS LQFP176-P-2424-0.50-BK Mirror finish 5 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times) ...
Page 45
... OKI Semiconductor REVISION HISTORY Document Date No. PEDL87V3116-01 Jan. 30, 2004 PEDL87V3116-02 Sep. 21, 2004 Page Previous Current Edition Edition – – Preliminary edition 1 – – PEDL87V3116-02 ML87V3116 Description 45/47 ...
Page 46
... OKI Semiconductor NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product ...