wm8150scds-r Wolfson Microelectronics plc, wm8150scds-r Datasheet - Page 23

• Manufacturer Part Number: wm8150scds-r
• Description: Single Channel 12-bit Cis/ccd Afe With 4-bit Wide Output
• Manufacturer: Wolfson Microelectronics plc

Production Data
Table 5 Register Control Bits
w
Setup
Register 5
Test
Register 1
Offset DAC
(Red)
Offset DAC
(Green)
Offset DAC
(Blue)
Offset DAC
(RGB)
PGA gain
(Red)
PGA gain
(Green)
PGA gain
(Blue)
PGA gain
(RGB)
REGISTER
BIT
3:1
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
NO
0
4
7
POSNNEG
VSMPDET
DACG[7:0]
PGAG[7:0]
DACR[7:0]
DACB[7:0]
PGAR[7:0]
PGAB[7:0]
VDEL[2:0]
DAC[7:0]
PGA[7:0]
NAME(S)
TCLK
BIT
DEFAULT
000
80
80
80
0
0
0
0
0
0
0 = Normal operation, signal on VSMP input pin is applied directly to
Timing Control block.
1 = Programmable VSMP detect circuit is enabled. An internal
synchronisation pulse is generated from signal applied to VSMP input pin
and is applied to Timing Control block.
When VSMPDET = 0 these bits have no effect.
When VSMPDET = 1 these bits set a programmable delay from the
detected edge of the signal applied to the VSMP pin. The internally
generated pulse is delayed by VDEL MCLK periods from the detected
edge.
See Figure 14, Internal VSMP Pulses Generated for details.
When VSMPDET = 0 this bit has no effect.
When VSMPDET = 1 this bit controls whether positive or negative edges
are detected:
0 = Negative edge on VSMP pin is detected and used to generate internal
timing pulse.
1 = Positive edge on VSMP pin is detected and used to generate internal
timing pulse.
See Figure 14 for further details.
0 = Normal Operation, OP[3:0] output ADC data.
1 = Internal Clock Test Mode. This allows internal timing signals to be
multiplexed onto the OP[3:0] pins as follows.
Red channel offset DAC value. Used under control of the INTM[1:0]
control bits.
Green channel offset DAC value. Used under control of the INTM[1:0]
control bits.
Blue channel offset DAC value. Used under control of the INTM[1:0]
control bits.
A write to this register location causes the red, green and blue offset DAC
registers to be overwritten by the new value
Determines the gain of the red channel PGA according to the equation:
Red channel PGA gain = [0.78+(PGAR[7:0]*7.57)/255]. Used under
control of the INTM[1:0] control bits.
Determines the gain of the green channel PGA according to the equation:
Green channel PGA gain = [0.78+(PGAG[7:0]*7.57)/255]. Used under
control of the INTM[1:0] control bits.
Determines the gain of the blue channel PGA according to the equation:
Blue channel PGA gain = [0.78+(PGAB[7:0]*7.57)/255]. Used under
control of the INTM[1:0] control bits.
A write to this register location causes the red, green and blue PGA gain
registers to be overwritten by the new value
OP[3]
OP[2]
OP[1]
OP[0]
PIN
DESCRIPTION
TCLK=0
OP[3]
OP[2]
OP[1]
OP[0]
PD Rev 4.1 February 2005
Video sample clock
Reset sample clock
ADC clock
INTVSMP
TCLK=1
WM8150
23