wm8150scds-r Wolfson Microelectronics plc, wm8150scds-r Datasheet - Page 11

• Manufacturer Part Number: wm8150scds-r
• Description: Single Channel 12-bit Cis/ccd Afe With 4-bit Wide Output
• Manufacturer: Wolfson Microelectronics plc

Production Data
CDS/NON-CDS PROCESSING
w
Figure 4 Reset Level Clamping and CDS Circuitry
Reset Level Clamping is controlled by register bit RLCINT. Figure 5 illustrates the effect of the
RLCINT bit for a typical CCD waveform, with CL applied during the reset period.
The RLCINT register bit is sampled on the positive edge of MCLK that occurs during each VSMP
pulse. The sampled level, high (or low) controls the presence (or absence) of the internal CL pulse on
the next reset level. The position of CL can be adjusted by using control bits CDSREF[1:0] (Figure 6).
Figure 5 Relationship of RLCINT, MCLK and VSMP to Internal Clamp Pulse, CL
The VRLC/VBIAS pin can be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits
RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit
RLCDACRNG. Alternatively, the VRLC/VBIAS pin can be driven externally by writing to control bit
VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin.
For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel
common mode noise. For CDS operation, the video level is processed with respect to the video reset
level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must
be set to 1 (default), this sets switch 2 into the position shown in Figure 4 and causes the signal
reference to come from the video reset level. The time at which the reset level is sampled, by clock
R
s
(CDSREF = 01)
/CL, is adjustable by programming control bits CDSREF[1:0], as shown in Figure 6.
INPUT VIDEO
ACYC/RLC
or RLCINT
EXTERNAL VRLC
MCLK
VSMP
CL
C
IN
1
VRLC/
VBIAS
RGB
VINP
Programmable Delay
X
1
RLC
CL
2
MCLK
X
TIMING CONTROL
VRLCEXT
RLC DAC
4-BIT
S/H
RLC on this Pixel
R
S
CDS
VSMP
CDS
RGB
0
S/H
V
S
INPUT SAMPLING
X
BLOCK
+
-
+
PD Rev 4.1 February 2005
FROM CONTROL
INTERFACE
TO OFFSET DAC
FROM CONTROL
INTERFACE
X
No RLC on this Pixel
WM8150
RGB
0
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