wm8150scds-r Wolfson Microelectronics plc, wm8150scds-r Datasheet - Page 15
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wm8150scds-r
Manufacturer Part Number
wm8150scds-r
Description
Single Channel 12-bit Cis/ccd Afe With 4-bit Wide Output
Manufacturer
Wolfson Microelectronics plc
Datasheet
1.WM8150SCDS-R.pdf
(26 pages)
Production Data
OUTPUT DATA FORMAT
w
The digital data output from the ADC is available to the user in 4-bit wide multiplexed. Latency of
valid output data with respect to VSMP is programmable by writing to control bits DEL[1:0]. The
latency for each mode is shown in the Operating Mode Timing Diagrams section.
Figure 10 shows the output data formats for Mode 1 and 3 – 6. Figure 11 shows the output data
formats for Mode 2. Table 2 summarises the output data obtained for each format.
Table 2 Details of Output Data Shown in Figure 10 and Figure 11.
FLAGS
The OVRNG flag that is output during nibble D indicates that the current output data was produced
by an input signal that exceeded the input range limit of the device. 1 = Out of range, 0 = within
range.
The CC[1:0] flags that are output during nibble D are used to indicate which set of offset and gain
registers have been used for the current data. CC[1:0] = 00 indicates Red, CC[1:0] = 01 indicates
Green and CC[1:0] = 10 indicates that the Blue offset and gain registers were applied during the
processing.
Figure 10 Output Data Formats
4+4+4+4-bit
FORMAT
OUTPUT
(nibble)
4+4+4-BIT
OUTPUT
(Modes 1, 3, 4)
MCLK
OUTPUT
OP[3:0]
PINS
A
B
C
A = d11, d10, d9, d8
B = d7, d6, d5, d4
C = d3, d2, d1, d0
D = 0, CC[1], CC[0], OVRNG
D
Figure 11 Output Data Formats
OUTPUT
(Mode 2)
4+4+4-BIT
OUTPUT
MCLK
PD Rev 4.1 February 2005
A B
A B
C D
WM8150
D
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