msm98s000 ETC-unknow, msm98s000 Datasheet - Page 6

• Manufacturer Part Number: msm98s000
• Description: 0.8m Mixed 3-v/5-v Gates Customer Structured Arrays
• Manufacturer: ETC-unknow

2. Make a floor plan for the design’s megacells.
Figure 2 shows an array base after placement of the optimized memory macrocells.
3. Place and route logic into the array transistors.
Figure 3 marks the area in which placement and routing is performed with light shading.
4
MSM38S/98S Data Sheet
- Add together all the area occupied by the required random logic and macrocells and select
- OKI Design Center engineers verify the master slice and review simulation.
- OKI Design Center engineers floorplan the array using OKI’s proprietary floorplanner and
- Using OKI CAD software, Design Center engineers remove the SOG transistors and replace
- OKI Design Center engineers use layout software and customer performance specifications
OKI SEMICONDUCTOR
the optimum array.
customer performance specifications.
them with diffused memory macrocells to the customer’s specifications.
to connect the random logic and optimized memory macrocells.
Figure 2. Optimized Memory Macrocell Floor Plan
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Figure 3. Random Logic Place and Route
Early mask high-density ROM
Mega macrocell
High-density RAM
Multi-port RAM