msm98s000 ETC-unknow, msm98s000 Datasheet - Page 15

• Manufacturer Part Number: msm98s000
• Description: 0.8m Mixed 3-v/5-v Gates Customer Structured Arrays
• Manufacturer: ETC-unknow

DESIGN PROCESS
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Manufacturing
Prototype
Scan Insertion (Optional)
Post-Layout Simulation
(Cadence DRACULA)
(Silvar Lisco Gards)
Netlist Conversion
(Cadence Verilog)
Floorplanning
Floorplanning
Schematics
(EDIF 200)
Verification
CDC
CDC
Layout
[1] OKI Circuit Data Check program (CDC) verifies logic design rules
[2] OKI Test Data Check program (TDC) verifies test vector rules
[3] OKI Test Pattern Language (TPL)
[4] Alternate Customer-OKI design interfaces available in addition to standard level 2
[5] Standard design process includes fault simulation
[1]
[1]
Test Program
Conversion
(Cadence Verifault or IKOS)
VHDL/HDL Description
Pre-Layout Simulation
(Cadence Verilog)
Fault Simulation
Figure 8. OKI Design Process
Simulation
[5]
(Synopsys Test Compiler)
Test Vector Conversion
Vector Generation
Automatic Test
Test Vectors
(OKI TPL
TDC
[2]
[3]
)
OKI SEMICONDUCTOR
Level 1
Level 2
Level 2.5
Level 3
MSM38S/98S Data Sheet
[4]
[4]
[4]
CAE Front-End
OKI Interface
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