msm98s000 ETC-unknow, msm98s000 Datasheet - Page 5

• Manufacturer Part Number: msm98s000
• Description: 0.8m Mixed 3-v/5-v Gates Customer Structured Arrays
• Manufacturer: ETC-unknow

ARRAY ARCHITECTURE
The primary components of a 0.8µm MSM38S/98S circuit include:
Each array has 16 dedicated corner pads for power and ground use during wafer probing, with four pads
per corner. The arrays also have separate power rings for the internal core functions (V
output drive transistors (V
MSM98S000 CSA Layout Methodology
The procedure to design, place, and route a CSA follows.
1. Select suitable base array frame from the available predefined sizes. To select an array size:
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• I/O base cells
• Configurable I/O pads for V
• V
• Separate power bus for output buffers
• Separate power bus for internal core logic and input buffers
• Core base cells containing N-channel and P-channel pairs, arranged in column of gates
• Isolated gate structure for reduced input capacitance and increased routing flexibility
Configurable I/O pads for
V
I/O (3.3 V), or I/O (5 V)
DD
DD
(3.3 V), V
- Identify the macrocell functions required and the minimum array size to hold the macrocell
and V
functions.
DD
SS
(5 V), V
pads dedicated to wafer probing
V
each corner for
wafer probing only
SS
DD
,
, V
SS
DDO
pads in
for 3 V and V
Figure 1. MSM38S/98S Array Architecture
I/O cells include
DD
level shifter
, V
SS
, or I/O (I/O in both 3V and 5V)
SSO
V
V
DD
).
SSO
Core Area
= 3.3 or 5 V
V
DDO
V
(3.3 V)
DDO
(5 V)
for internal core logic
Separate power bus
Separate power bus over
I/O cell for output buffers
(V
DDO
(3.3 V), V
OKI SEMICONDUCTOR
DDO
MSM38S/98S Data Sheet
(5 V), V
of Gates
Column
SSO
DDC
Four-transistor
basic core cell
)
and V
SSC
) and
3