msm98s000 ETC-unknow, msm98s000 Datasheet - Page 3

• Manufacturer Part Number: msm98s000
• Description: 0.8m Mixed 3-v/5-v Gates Customer Structured Arrays
• Manufacturer: ETC-unknow

MSM38S0000/MSM98S000
0.8µm Mixed 3-V/5-V Sea of Gates and Customer Structured Arrays
DESCRIPTION
OKI’s 0.8µm ASIC products, specially designed for mixed 3-V/5-V applications, are now available in both
Sea Of Gates (SOG) and Customer Structured Array (CSA) architectures. Both the SOG-based MSM38S
Series and the CSA-based MSM98S Series use a three-layer-metal process on 0.8µm drawn (0.6µm L-effec-
tive) CMOS technology. The semiconductor process is adapted from OKI’s production-proven 16-Mbit
DRAM manufacturing process.
Ideal for low-power portable applications, the MSM38S/98S are constructed with separate power busses
for internal core logic and configurable I/O functions. Altogether, the architecture provides maximum
flexibility, meeting the needs of all 3-V, 5-V, and mixed 3-V/5-V signal requirements.
The MSM38S SOG Series is available in seven sizes with up to 420 I/O pads and over 135,000 usable gates.
SOG array sizes are designed to fit the most popular quad flat pack (QFP) packages, such as 100-, 136-,
160-, and 208-pin QFPs. MSM38S SOG-based designs are therefore ideal for pad-limited circuits that
require rapid prototyping turnaround times.
The MSM98S CSA Series is an all-mask-level superset of the SOG series, available in 29 sizes. The CSA
offerings combine the SOG architecture’s logic flexibility with the higher integration yielded by optimized
diffusion for faster and more compact memory blocks. The MSM98S is ideal for core-limited applications
or circuits with large and/or multiple memory functions. Customer modification to the structure of any
of the 29 predefined masterslices, rather than creation of a new masterslice every time, improves the pro-
totyping turnaround time over cell-based manufacturing techniques.
Both product families are supported by OKI’s proprietary MEMGEN tool which quickly and easily gen-
erates SOG memories (for the MSM38S) as well as optimized memories for the MSM98S Series. The fam-
ilies also feature floorplanning to control pre-layout timing, clock-skew management software that
guarantees worst-case clock skew of 1 ns or less, and scan-path design techniques that support ATVG for
fault coverage approaching 100%.
FEATURES
• 0.8µm drawn three-layer metal CMOS
• Mixed 3-V/5-V operation for low power and high
• SOG and CSA architecture availability
• Clock tree cells with 1.0-ns clock skew, worst-case
• Usable density from 6.5k to 135k gates
• I/Os may be VSS, 3 V, 5 V, VDD, CMOS, TTL, and 3-
speed
(fan-out = 2000 at 70 MHz)
state, with 2-mA to 48-mA drive
• I/O level shifter cells, allowing any buffer (input,
• Slew-rate-controlled outputs for low radiated noise
• User-configurable single and multi-port memories
• Specialized 3-V and 5-V macrocells, including phase-
• Floorplanning for front-end simulation and back-end
• JTAG boundary scan and scan-path ATVG
output, or bidirectional) to interface with 3 V or 5 V
locked loop, and PCI cells
layout controls
OKI SEMICONDUCTOR
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