msm98s000 ETC-unknow, msm98s000 Datasheet - Page 13

• Manufacturer Part Number: msm98s000
• Description: 0.8m Mixed 3-v/5-v Gates Customer Structured Arrays
• Manufacturer: ETC-unknow

The clock-skew management scheme is described in detail in the 0.8µm Technology Clock Skew Management
Application Note .
OUTPUT DRIVER MACROCELLS FOR SLEW RATE CONTROL
The slew-rate-control output driver macrocells reduce both simultaneous-switching noise and output-
ringing noise. The output transistors are split into two sets; first, one set of output transistors drive the
output pads, then, after the output passes the threshold, the second set of output transistors drive the I/O
pads.
Figure 6 below shows output drivers configured for slew-rate control. All outputs with a drive of 8 mA or
more are available with slew-rate control.
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• Dynamic sub-trunk allocation
• Single clock tree driver logic symbol
• Single-level clock drivers
• Automatic branch length minimization
• Dynamic driver placement
• Up to four clock trunks
From Internal Node
Pad
Input Buffer
Figure 6. Slew Rate Control Output Buffer
Clocked Cell
Figure 5. Clock Tree Structure
Output Transistors
Branch
First Set of
Switch
Main Trunk
Sub Trunk
Output Transistors
Second Set of
Clock Tree
Driver Macrocell
Clock Drivers
OKI SEMICONDUCTOR
MSM38S/98S Data Sheet
Output Pad
11