ml7037 Oki Semiconductor, ml7037 Datasheet - Page 8

• Manufacturer Part Number: ml7037
• Description: Ml7037-003 Dual Echo Canceler & Noise Canceler With Dual Codec For Hands-free
• Manufacturer: Oki Semiconductor

Not for Publication
PIN FUNCTIONAL DESCRIPTION
AIN0N, AIN0P, AGSX0, AIN1N, AGSX1
These are the acoustic analog input and level tuning pins. The AIN0N pin and the AIN1N pin are connected to the
inverting input of the internal amp (AMP2、AMP1), and the AIN0P pin is connected to the non-inverting input of
the internal amp (AMP2). The AGSX0 pin and the AGSX1 pin are connected to the internal amp (AMP2、AMP1).
For the way to tune the level, refer to Figure 3 Analog Interface.
During power-down mode (PDN pin = logic ‘0’ or SPDN-bit [CR0-B7] = ‘1’), the AGSX0 pin and the AGSX1
pin go to a high impedance state.
(Note) When the acoustic side LSI-internal amplifier (AMP2) is not used, connect the AIN0P pin and the
(Note) Please refer to the application circuit example when the acoustic side LSI-internal amplifier (AMP2) is
OKI Semiconductor
AVREF pin and short the AIN0N pin and the AGSX0 pin.
used as a single-end input.
Gain=(R2/R1) x (R4/R3)
VAGSX1,0 ≦ 1.3Vpp
10k ≦ R2 ≦ 510k
10k ≦ R4 ≦ 510k
VLVFRO ≦ 1.3Vpp
Buffer Amp 10F
VAVFRO ≦ 1.3Vpp
Gain=R6/R5
10k ≦ R6 ≦ 510k
VLGSX ≦ 1.3Vpp
R3
C1
C1
C3
C4
C4
C2
R1
R1
R5
R4
R2
R2
R6
0.1F
Figure 3 Analog Interface
AGSX1
AGSX0
AVREF
AVFRO
LVFRO
AIN1N
AIN0N
AIN0P
LGSX
LINN
(AMP1)
(AMP2)
(AMP3)
Gain-Max（AMP2）≦10 times(+20dB)
(AMP4)
(AMP5)
Gain-Max（AMP1）≦5 times (+13.97dB)
Gain-Max（AMP3）≦10 times(+20dB)
PGA
PGA
AVREF
A/D
D/A
A/D
D/A
PEDL7037-003-05Zz_Digest
ML7037-003
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