ml7037 Oki Semiconductor, ml7037 Datasheet - Page 11

• Manufacturer Part Number: ml7037
• Description: Ml7037-003 Dual Echo Canceler & Noise Canceler With Dual Codec For Hands-free
• Manufacturer: Oki Semiconductor

Not for Publication
SYNC
This is the 8 kHz sync clcok I/O pin for PCM interface. When the internal clock mode is selected by the CLKSEL
pin = logic ‘0’, this pin outputs 8kHz sync clocks synchronizing with the BCLK. When the external clock mode is
selected by the CLKSEL pin = logic ‘1’, input 8kHz clocks to this pin in synchronization with the BCLK.
When the SYNCSEL pin is logic ‘0’, this pin outputs/expects to have sync clocks in a long frame sync timing;
whereas, when the SYNCSEL pin is logic ‘1’, this pin outputs/expects to have sync clocks in a short frame sync
timing.
BCLK
This is the shift clock I/O pin for PCM interface. When the internal clock mode is selected by the CLKSEL pin =
logic ‘0’, this pin outputs 64kHz in µ-law PCM mode or 128kHz in 16-bit linear PCM mode. When the external
clock mode is selected by the CLKSEL pin = logic ‘1’, input shift clocks to this pin in synchronization with the
SYNC. The input frequency must be between 64 kHz and 2048 kHz in µ-law PCM mode and 128 kHz and 2048
kHz in 16-bit linear PCM mode.
CLKSEL
This pin selects internal or external clock modes for PCM interface.
A logic ‘0’ selects the internal clock mode where the SYNC pin and the BCLK pin output clocks so that this LSI
could works as a clock master device in your system.
A logic ‘1’ selects the external clock mode where this LSI needs the SYNC and the BCLK externally so that this
LSI could works as a clock slave device in your system.
If PCM digital interface is not used, set this pin to a logic ‘0’ to select internal clock mode.
(Note) The change of the input state of this pin must be made during power-down state ( PDN pin = logic ‘0’ or
SYNCSEL
This is the frame sync timing selection pin for PCM interface.
A logic “0” selects long frame sync timing, and a logic “1” selects short frame sync timing.
Refer Figure 5 to Figure8 for the timing.
(Note) The change of the input state of this pin must be made during power-down state (PDN pin = logic ‘0’ or
PCMSEL
This is the coding format selection pin for PCM interface for the PCMO-pin output and the PCMI-pin input signal.
A logic ‘0’ selects 16-bit linear PCM (2’s complement) coding format, and a logic ‘1’ selects µ-law PCM coding
format.
The full scale table for both formats are shown below;
16bit Linear PCM (2’s complement) Full Scale Table
-law PCM Full Scale Table
(Note) If PCM interface is not used, set this pin to a logic ‘0’.
(Note) The change of the input state of this pin must be made during power-down state (PDN pin = logic ‘0’ or
OKI Semiconductor
+ Full Scale
+ Full Scale
- Full Scale
- Full Scale
Level
Level
+1
+0
-1
-0
0
SPDN-bit [CR0-B7] = ‘1’) or during initial mode.
SPDN-bit [CR0-B7] = ‘1’) or during initial mode.
SPDN-bit [CR0-B7] = ‘1’) or during initial mode.
MSB
MSB
0
0
0
1
1
1
1
0
0
1
0
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
LSB
1
0
0
1
0
0
1
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
PEDL7037-003-05Zz_Digest
1
0
0
1
0
1
0
0
1
0
ML7037-003
1
0
0
1
0
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LSB
1
1
0
1
0