ml7037 Oki Semiconductor, ml7037 Datasheet - Page 18

• Manufacturer Part Number: ml7037
• Description: Ml7037-003 Dual Echo Canceler & Noise Canceler With Dual Codec For Hands-free
• Manufacturer: Oki Semiconductor

Not for Publication
GPIB0
This is a general-purpose input port pin.
(Note) If this pin is not used, set this pin to a logic ‘0’.
GPOC0, GPOC1, GPOC2, GPOC3, GPOC4, GPOC5, GPOC6, GPOC7
These are general-purpose output port pins.
(Note) If these pins are not used, leave these pins floating.
DVDD0, DVDD1, AVDD
These are power supply pins. The DVDD0 and the DVDD1 are connected to digital circuits and the AVDD is
connected to analog circuits in this LSI via the built-in regulator.
Connect them common in the shortest distance, and insert a 10 µF bypass capacitor (a tantalum capacitor
[recommendation] or an aluminum electrolytic capacitor) and a 0.1 µF capacitor (laminating ceramic type) in
parallel between these pins and the DGND0, 1 pins and the AGND0, 1 pins respectively.
DGND0, DGND1, AGND0, AGND1
These are ground pins. The DGND0 pin and the DGND1 pin are connected to the ground of digital circuits in this
LSI. The AGND0 pin and the AGND1 pin are connected to the ground of analog circuits in this LSI. Connect them
common in the shortest distance
REGOUT0, REGOUT 1
These are the built-in regulator output pins (2.6V approx.).
Insert a 10 µF capacitor (a tantalum capacitor [recommendation] or an aluminum electrolytic capacitor) and a 0.1
µF capacitor (laminating ceramic type) in parallel between the REGOUT0 pin and the DGND0 pin.
Insert a 0.1 µF capacitor (laminating ceramic type) in parallel between the REGOUT1 pin and the DGND1 pin.
VBG
This is an output pin for a reference voltage of the built-in regulator (1.2V approx.).
Insert a 150 pF (approx.) laminating ceramic capacitor between the this pin and the DGND0.
PDN
This is the power-down reset control input pin.
A logic ‘0’ executes the power-down reset.
When a logic ‘1’ is input to this pin, this LSI is in a normal operation.
This execution also initializes all of this LSI including the control registers, the internal data memories, the filter
coefficients of the echo cancellers and those of the noise cancellers.
(Note) The negative logic of this pin is ORed with the SPDN-bit [CR0-B7].
(Note) To avoid unstable operations, right after the power-up, execute the power-down rest with this pin (not
(Note) When an ORed logic of the AVREFEN pin and the AVREFEN-bit [CR16-B7] are logic ‘1’, the AVREF
RST
This is an input pin to initialize the filter coefficients of the echo cancellers and the noise canceller and the ALC
acquired gain.
A logic ‘0’ executes the initialization. For a normal operation, give this pin a logic ‘1’.
During the reset state, no speech signals are output. Control registers are preserved.
Execute the initialization in cases where the echo path changes (due to line switching during a telephone
conversation, etc.), or for another call.
(Note) The negative logic of this pin is ORed with the RST-bit [CR0-B6].
(Note) The change of the input state to these pins is detected at the rising edge of the SYNC clock so that the
(Note) The execution of this reset during a call may cause minor noises due to interruption at an arbitrary point in
OKI Semiconductor
with the SPDN-bit [CR0-B7]). The master clock input to the XI pin and the REGOUT output higher than
90% of the normal state are prerequisite to secure the power-down reset.
and analog output amps keep powered up even during the power-down state.
change of the input state to this pin less than 250 s may not be reflected as the LSI behavior.
a sequence of PCM codes so that an execution of the reset is recommended to be made in a silent state.
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