ml7037 Oki Semiconductor, ml7037 Datasheet - Page 12

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ml7037

Manufacturer Part Number
ml7037
Description
Ml7037-003 Dual Echo Canceler & Noise Canceler With Dual Codec For Hands-free
Manufacturer
Oki Semiconductor
Datasheet

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PEDL7037-003-05Zz_Digest
OKI Semiconductor
ML7037-003
PCMI
This is the receive PCM data input pin on the line-side. This input data is shifted at the falling edge of the BCLK.
The PCM coding format can be selected between 16-bit linear PCM (2’s complement) coding format and µ-law
PCM coding format with the PCMSEL pin or the PCMSEL-bit [CR0-B4].
The PCM frame sync timing can be selected between a long frame sync and a short frame sync with the SYNCSEL
pin.
Refer Figure 5 to Figure8 for the timing.
(Note) If this pin is not used, set this pin to a logic ‘0’.
(Note) The change of the input state of this pin must be made during power-down state ( PDN pin = logic ‘0’ or
SPDN-bit [CR0-B7] = ‘1’) or during initial mode.
PCMO
This is the receive PCM data output pin on the line-side. This output data is shifted at the rising edge of the BCLK.
During power-down mode (PDN pin = logic ‘0’ or SPDN-bit [CR0-B7] = ‘1’) and initial mode or while effective
PCM data bits are not being output, this pin goes to a high impedance state.
The PCM coding format can be selected between 16-bit linear PCM (2’s complement) coding format and -law
PCM coding format with the PCMSEL pin or the PCMSEL-bit [CR0-B4].
The PCM frame sync timing can be selected between a long frame sync and a short frame sync with the SYNCSEL
pin.
Refer Figure 5 to Figure8 for the timing.
Not for Publication
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