ispgal22v10av Lattice Semiconductor Corp., ispgal22v10av Datasheet - Page 6

• Manufacturer Part Number: ispgal22v10av
• Description: In-system Programmable Low Voltage E2 Cmos Pld Generic Array Logic ?
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
via the parallel port of a PC. Alternatively, the software can output files in formats understood by common auto-
mated test equipment. This equipment can then be used to program ispGAL22V10A devices during the testing of a
circuit board.
Security Bit
A programmable security bit is provided on the ispGAL22V10A devices as a deterrent to unauthorized copying of
the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a
device programmer, securing proprietary designs from competitors. Programming and verification are also
defeated by the security bit. The bit can only be reset by erasing the entire device.
Hot Socketing
The ispGAL22V10A devices are well-suited for applications that require hot socketing. Hot socketing a device
requires that the device, during power-up and down, tolerate active signals on the I/Os and inputs without being
damaged. Additionally, it requires that the effects of I/O pin loading be minimal on active signals. The
ispGAL22V10A devices provide this capability for input voltages in the range of 0V to 3.0V.
Power-up Reset
Circuitry within the ispGAL22V10A provides a reset signal to all registers during power-up. All internal registers will
have their Q outputs set low after a specified time (tpr, 1µs typical). As a result, the state on the registered output
pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the out-
put pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing
diagram for power-up is shown above. Because of the asynchronous nature of system power-up, some conditions
must be met to provide a valid power-up reset of the ispGAL22V10A. First, the Vcc rise must be monotonic. Sec-
ond, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset
within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback
path setup times have been met. The clock must also meet the minimum pulse width requirements.
Figure 6. Timing Diagram for Power-up
INTERNAL REGISTER
OUTPUT REGISTER
OUTPUT REGISTER
ACTIVE HIGH
ACTIVE LOW
Q - OUTPUT
C L K
V c c
Vcc (min.)
6
t
pr
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
Device Pin
Reset to Logic "0"
ispGAL22V10AV/B/C Data Sheet
t
wl
t
su