clc2500 Cadeka Microcircuits LLC., clc2500 Datasheet - Page 5

• Manufacturer Part Number: clc2500
• Description: Dual Ultrafast Voltage Comparator
• Manufacturer: Cadeka Microcircuits LLC.

Advance Data Sheet
Timing Information
The timing diagram for the comparator is shown in Figure
1. If LE is high and LE low in the CLC2500, the comparator
tracks the input difference voltage. When LE is driven low
and LE high, the comparator outputs are latched into their
existing logic states.
The leading edge of the input signal (which consists of a
20 mV overdrive voltage) changes the comparator output
after a time of tpdL or tpdH (Q or Q). The input signal
must be maintained for a time t
LE falling edge and LE rising edge and held for time t
after the falling edge for the comparator to accept data.
After t
is strobed again. A minimum latch pulse width of t
needed for strobe operation, and the output transitions
occur after a time of t
The set-up and hold times are a measure of the time
required for an input signal to propagate through the first
stage of the comparator to reach the latching circuitry.
Input signals occurring before t
those occurring after t
between t
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H
, the output ignores the input status until the latch
S
and t
H
may not be detected.
pLOH
H
will not be detected. Changes
or t
pLOL
S
S
will be detected and held;
(set-up time) before the
.
Figure 1 - Timing Diagram
pL
is
H
Switching Terms
Symbol Description
t
t
t
V
t
t
t
t
pdH
pdL
pdLOH
pLOL
H
pL
S
OD
INPUT TO OUTPUT HIGH DELAY – the propaga-
tion delay measured from the time the input signal
crosses the reference (± the input offset voltage) to
the 50% point of an output LOW to HIGH transition
INPUT TO OUTPUT LOW DELAY – the propaga-
tion delay measured from the time the input signal
crosses the reference (± the input offset voltage) to
the 50% point of an output HIGH to LOW transition
LATCH ENABLE TO OUTPUT HIGH DELAY – the
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to
the 50% point of an output LOW to HIGH transition
VOLTAGE OVERDRIVE – the difference between the
differential input and reference input voltages
LATCH ENABLE TO OUTPUT LOW DELAY – the
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to
the 50% point of an output HIGH to LOW transition
MINIMUM HOLD TIME – the minimum time after
the negative transition of the Latch Enable signal
that the input signal must remain unchanged in
order to be acquired and held at the outputs
MINIMUM LATCH ENABLE PULSE WIDTH – the
minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change
MINIMUM SET-UP TIME – the minimum time before
the negative transition of the Latch Enable signal
that an input signal change must be present in
order to be acquired and held at the outputs
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