CDK8307 Cadeka Microcircuits LLC., CDK8307 Datasheet
CDK8307
Related parts for CDK8307
CDK8307 Summary of contents
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... The CDK8307 is designed to easily interface with field-programmable gate arrays (FPGAs) from several vendors. The very low startup times of the CDK8307 allow significant power reduction in duty-cycled systems, by utilizing the Sleep Mode or Power Down Mode when the receive path is idle. ...
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... Electrical Characteristics ...................................... 10 Electrical Characteristics – CDK8307A ................ 10 Electrical Characteristics – CDK8307B ................ 11 Electrical Characteristics – CDK8307C ................ 11 Electrical Characteristics – CDK8307D ................ 12 Electrical Characteristics – CDK8307E ................ 12 Digital and Timing Electrical Characteristics ...... 13 LVDS Timing Diagrams ......................................... 14 Figure 1. 12-bit Output, DDR Mode ......................... 14 Figure 2. 14-bit Output, DDR Mode ......................... 14 Figure 3. 12-bit Output, SDR Mode ......................... 14 Figure 4 ...
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... CDK8307BILP64B2** 40MSPS QFN-64 CDK8307CITQ80* 50MSPS TQFP-80 CDK8307CILP64* 50MSPS QFN-64 CDK8307CILP64B2** 50MSPS QFN-64 CDK8307DITQ80* 65MSPS TQFP-80 CDK8307DILP64* 65MSPS QFN-64 CDK8307DILP64B2** 65MSPS QFN-64 CDK8307EITQ80* 80MSPS TQFP-80 CDK8307EILP64* 80MSPS QFN-64 CDK8307EILP64B2** 80MSPS QFN-64 Moisture sensitivity level for all parts is MSL-2A. *Preliminary. **Possible future product, contact CADEKA for more information. ...
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... AVSS CLKN 9 39 IN5 CLKP 10 AVDD 11 38 IP5 AVDD 12 37 AVSS DVSS 13 36 DVSS 35 DVDD DVDD 14 34 D4N 15 D8N D4P 16 33 D8P CDK8307 TQFP-80 48 AVDD 47 IP6 46 IN6 45 AVDD 44 IN5 43 IP5 42 AVDD QFN- CSN 39 SDATA 38 SCLK 37 AVDD 36 DCVSS 35 DVDD 34 D5P ...
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PRELIMINARY Data Sheet Pin Assignments Pin No. QFN-64 49, 50 37, 40, 43, 46 12, 14 ...
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PRELIMINARY Data Sheet Pin Assignments (Continued) Pin No. 26 51, 54, 55 QFN-64 (B2 version: AD9222 pinout option 11, 12, 37, 42, 45, 48, 51, 59, 62 ...
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PRELIMINARY Data Sheet Pin Assignments (Continued) Pin No TQFP 1, 7, 14, 47, 54, 60, 63 ...
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PRELIMINARY Data Sheet Pin Assignments (Continued) Pin No. 15, 17, 18, 26, 36, 43, 44 ...
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PRELIMINARY Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for ...
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... Digital Supply Voltage (up to 65MSPS) DVDD Digital Supply Voltage (above 65MSPS) OVDD Digital CMOS Input Supply Voltage Electrical Characteristics - CDK8307A (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted) Symbol Parameter Performance SNR ...
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... Sleep Mode Dissipation Sleep Channel Mode Dissipation Sleep Channel Mode Savings Clock Inputs Maximum Conversion Rate Minimum Conversion Rate Electrical Characteristics - CDK8307C (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 50MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted) Symbol Parameter Performance SNR ...
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... Sleep Mode Dissipation Sleep Channel Mode Dissipation Sleep Channel Mode Savings Clock Inputs Maximum Conversion Rate Minimum Conversion Rate Electrical Characteristics - CDK8307E (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 12-bit output, unless otherwise noted) Symbol Parameter Performance SNR ...
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PRELIMINARY Data Sheet Digital and Timing Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, unless otherwise noted) Symbol Parameter Clock Inputs Duty Cycle Compliance Input range, differential Input range, sine Input range, CMOS Input common mode voltage ...
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PRELIMINARY Data Sheet LVDS Timing Diagrams Analog Input ADC Clock LCLKP LCLKN FCLKN FCLKP D10 D11 D0 Dxx<1:0> N-2 N-2 N-1 Analog Input ADC Clock LCLKP LCLKN FCLKN FCLKP D0 D1 Dxx<1:0> N-1 N-1 Analog Input ADC Clock LCLKP LCLKN ...
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... Data hold time h Register Initialization Before CDK8307 can be used, the internal registers must be initialized to their default values and power down must be activated. This can be done immediately after applying supply voltage to the circuit. Register initialization can be done in one of two ways applying a low-going pulse (minimum 20ns) on the RESETN pin (asynchronous). ...
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PRELIMINARY Data Sheet Serial Register Map Table 2. Summary of Functions Supported by the Serial Interface Name Description Software reset. rst This bit is self-clearing pd_ch<8:1> Channel-specific power-down sleep Go to sleep-mode power-down Configures the PD pin ...
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PRELIMINARY Data Sheet Table 2. Summary of Functions Supported by the Serial Interface (Continued) Name Description Controls the phase of LCLK phase_ddr<1:0> output relative to data pat_deskew Enable deskew pattern mode pat_sync Enable sync pattern mode Binary two's complement btc_mode ...
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PRELIMINARY Data Sheet Setting pd_ch<n> = '1', powers down channel <n> of the ADC. Setting sleep = '1', powers down the entire chip, except the band-gap reference circuit. Setting pd = '1' completely powers down the chip, including the band-gap ...
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PRELIMINARY Data Sheet Table 7. LVDS Internal Termination Programmability Name Description en_lvds_term Enables internal termination for LVDS buffers term_lclk<2:0> Programmable termination for LCLKN and LCLKP buffers term_ Programmable termination for frame<2:0> FCLKN and FCLKP buffers term_dat<2:0> Programmable termination for DxP ...
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... Enable sync pattern mode To ease the LVDS synchronization setup of CDK8307, several test patterns can be set up on the outputs. Normal ADC data are replaced by the test pattern in these modes. Setting en_ramp to '1' sets up a repeating full-scale ramp pattern on all data outputs. The ramp starts at code zero and is increased 1LSB every clock cycle. It returns to zero code and starts the ramp again after reaching the full-scale code ...
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... SDR mode The output interface of CDK8307 is normally a DDR interface, with the LCLK rising and falling edge transitions in the middle of alternate data windows. The phase for LCLK can be programmed relative to the output frame clock and data using bits phase_ddr< ...
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PRELIMINARY Data Sheet PHASE_DDR<1:0>=’00’ = 270° FCLKN FCLKP LCLKP LCLKN Dxx<1:0> PHASE_DDR<1:0>=’10’ = 90° (Default) FCLKN FCLKP LCLKN LCLKP Dxx<1:0> The device can also be made to operate in SDR mode by setting the en_sdr bit to '1'. The bit ...
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... To ease timing in the receiver when using multiple ADC chips, the CDK8307 has the option to adjust the timing of the output data and the frame clock. The propagation delay with respect to the ADC input clock can be moved one LVDS clock cycle forward or backward, by using lvds_advance and lvds_delay , respectively ...
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PRELIMINARY Data Sheet Table 16. Register Values with Corresponding Change in Full-Scale Range fs_cntrl <5:0> 111111 ... 100001 100000 011111 ... 000000 Table 17. Clock Frequency Name Description clk_freq<1:0> Input clock frequency To optimize startup time a register is provided ...
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PRELIMINARY Data Sheet Table 20. Performance Control Settings performance_control <2:0> 100 101 110 111 000 (default) 001 010 011 The ext_vcm_bc register controls the driving strength in the buffer supplying the voltage on the VCM pin. If this pin is ...
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... AVDD and AVSS, while the digital set is identified by DVDD and DVSS. Recommended Usage Analog Input The analog input to the CDK8307 is a switched capacitor track-and-hold amplifier optimized for differential opera- tion. Operation at common mode voltages at mid supply is recommended even if performance will be good for the ranges specified ...
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PRELIMINARY Data Sheet AC-Coupling A signal transformer or series capacitors can be used to make an AC-coupled input network. Figure 11 shows a recommended configuration using a transformer. Make sure that a transformer with sufficient linearity is selected, and that ...
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... PRELIMINARY Data Sheet Clock Input and Jitter Considerations Typically high-speed ADCs use both clock edges to generate internal timing signals. In the CDK8307 only the rising edge of the clock is used. Hence, input clock duty cycles between 20% and 80% is acceptable. The input clock can be supplied in a variety of formats. ...
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PRELIMINARY Data Sheet Mechanical Dimensions QFN-64 A aaa Pin 1 ID 0.05 Dia. 1.14 bbb 1.14 TOP VIEW Pin 1 ID 0.45 Dia. 0. BOTTOM VIEW ©2009 CADEKA Microcircuits LLC aaa ...
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... CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2009 by CADEKA Microcircuits LLC. All rights reserved. Symbol ...