CDK1304 Cadeka Microcircuits LLC., CDK1304 Datasheet
CDK1304
Related parts for CDK1304
CDK1304 Summary of contents
Page 1
... CMOS processing technologies to achieve its advanced performance. Inputs and outputs are TTL/CMOS- compatible to interface with TTL/CMOS logic systems. Output data format is straight binary. The CDK1304 is available in 28-lead SOIC and 32-lead small (7mm square) TQFP packages over the commercial temperature range. Pb-Free RoHS Compliant ...
Page 2
... Reference Low Sense Reference Low Force Calibration Reference Analog Input Analog V DD Digital V DD Digital Ground Input Clock ƒ (TTL) CLK Output Enable Tri-State Data Output, (D0 = LSB) Tri-State Output Overrange Data Valid Output Digital Output Supply Digital Output Ground No Connect CDK1304 www.cadeka.com 2 ...
Page 3
Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper ...
Page 4
Data Sheet Electrical Characteristics ( Min A Max DD DD symbol parameter Resolution DC Performance DLE Differential Linearity Error ILE Integral Linearity Error No Missing Codes Analog Input Input Voltage ...
Page 5
Data Sheet Electrical Characteristics ( Min A Max DD DD symbol parameter SFDR Spurious Free Dynamic Range Differential Phase Differential Gain Digital Inputs Logic “1“ Voltage (1) Logic “0“ Voltage ...
Page 6
Data Sheet Specification Definitions aperture Delay Aperture delay represents the point in time, relative to the rising edge of the CLOCK input, that the analog input is sampled. aperture Jitter The variations in aperture delay for successive samples. Differential Gain ...
Page 7
... Figure 2. Timing Diagram 2 ©2008 CADEKA Microcircuits LLC Description Conversion Time CLK Period CLK High Duty Cycle CLK Low Duty Cycle CLK to Output Delay (15pF load) CLK to DAV CDK1304 Figure 3. Typical Interface Circuit Diagram Table 1. Timing Parameters sym Min typ Max units ...
Page 8
... Voltage Reference The CDK1304 requires the use of a single external voltage reference for driving the high side of the reference ladder. It must be within the range 5V. The lower side of the ladder is typically tied to AGND (0 ...
Page 9
... The drive requirements for the analog inputs are very minimal when compared to most other converters due to the CDK1304 extremely low input capacitance of only 5pF and very high input resistance of 50kΩ. The analog input should be protected through a series resistor and diode clamping circuit as shown in Figure 7. ...
Page 10
... This board includes a reference circuit, clock driver circuit, output data latches, and an on-board reconstruction of the digital data. An application note describing the opera- tion of this board, as well as information on the testing of the CDK1304, is also available. Contact the factory for price and availability. Output Code D9- 1Ø ...
Page 11
... CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved. Symbol ...