ht82a523r Holtek Semiconductor Inc., ht82a523r Datasheet - Page 24

• Manufacturer Part Number: ht82a523r
• Description: Ht82a523r -- Usb 2.0 Full Speed 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

MISC register combines a command and status to control the desired endpoint FIFO action and to show the status of
the desired endpoint FIFO. The MISC will be cleared by USB reset signal.
Rev. 1.30
Bit No.
Bit No.
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
REQUEST
DMASEL
SETCMD
READY
CLEAR
CRCF
Label
ASET
Label
LEN0
DMA
ERR
OUT
NAK
EOT
NMI
TX
IN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
This bit is used to configure the SIE to automatically change the device address with
the value stored in the AWR register. When this bit is set to 1 by firmware, the SIE
will update the device address with the value stored in the AWR register after the PC
host has successfully read the data from the device by IN operation. Otherwise,
when this bit is cleared to 0 , the SIE will update the device address immediately af-
ter an address is written to the AWR register. So, in order to work properly, firmware
has to clear this bit after the next valid SETUP token is received.
This bit is used to indicate there are some errors occurred during the FIFO0 is ac-
cessed. This bit is set by SIE and should be cleared by firmware.
This bit is used to indicate there are OUT token (except for the OUT zero length token)
that have been received. The firmware clears this bit after the OUT data has been
read. Also, this bit will be cleared by SIE after the next valid SETUP token is received.
This bit is used to indicate that the current USB receiving signal from the PC host is
IN token. (1=IN token; 0=Non IN token)
This bit is used to indicate that the SIE has transmitted a NAK signal to the host in re-
sponse to the PC host IN or OUT token. (1=NAK signal; 0=Non NAK signal)
Error condition failure flag include CRC, PID, no integrate token error, CRCF will be
set by hardware and the CRCF need to be cleared by firmware.
Token Package active flag, low active.
NAK token interrupt mask flag. If this bit is set, when the device sent a NAK token to
the host, interrupt will not occur. Otherwise, when this bit is cleared, and the device
sent a NAK token to the host, it will enter the interrupt subroutine. The NMI is de-
signed for all endpoints.
After selecting the desired endpoint, FIFO can be requested by setting this bit as high
active. Afterwards, this bit must be set low.
This indicates the direction and transition end which the MCU accesses. When set
as logic 1, the MCU writes data to FIFO. Afterwards, this bit must be set to logic 0 be-
fore terminating request to indicate transition end. For reading action, this bit must be
set to logic 0 to indicate that the MCU wants to read and must be set to logic 1 af-
terwards.
This indicates an MCU clear requested FIFO, even if the FIFO is not ready. After
clearing the FIFO, USB interface will send force_tx_err to tell Host that data un-
der-run if Host want to read data.
1: Enable SBDR of the serial interfaces (which is pin-shared with port E or port C) be-
ing written to FIFO3 directly.
0: Disable SBDR of the serial interfaces (which is pin-shared with port E or port C)
being written to FIFO3 directly. SPI interfaces can be controlled by MCU and MCU
can transmit or receive data by writing or reading SBDR. It is allowed changing from
1 to 0 when the FIFO is not full.
0: Serial interface (pin-shared with port E) uses the DMA function.
1: Serial interface 2 (pin-shared with port C) uses the DMA function.
To show that the data in FIFO is setup command. This bit will last this state until next
one entering the FIFO. (1=SETCMD token; 0=Non SETCMD token)
To tell that the desired FIFO is ready to work.
(1=Ready to work; 0=Non ready to work)
To tell that host sent a 0-sized packet to MCU. This bit must be cleared by read action
to corresponding FIFO. (1=Host sent a 0-sized packet)
MISC (26H) Definitions
SIES (25H) Definitions
24
Function
Function
HT82A523R
May 13, 2008