ht82a523r Holtek Semiconductor Inc., ht82a523r Datasheet - Page 11

• Manufacturer Part Number: ht82a523r
• Description: Ht82a523r -- Usb 2.0 Full Speed 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

When the interrupt is enabled, the stack is not full and
the external interrupt is active, a subroutine call to loca-
tion 10H will occur. The interrupt request flag (USBF)
and EMI bits will be cleared to disable other interrupts.
When PC Host access the FIFO of the HT82A523R, the
corresponding request bit of USR is set, and a USB in-
terrupt is triggered when the corresponding interrupt is
enabled. So user can easily determine which FIFO is
accessed. When the interrupt has been served, the cor-
responding bit should be cleared by firmware. When the
HT82A523R receives a USB Suspend signal from the
Host PC, the suspend line (bit0 of the USC) of the
HT82A523R is set and a USB interrupt is also triggered.
Also when the HT82A523R receives a Resume signal
from the Host PC, the resume line (bit3 of the USC) of
the HT82A523R is set and a USB interrupt is triggered.
Whenever a USB reset signal is detected, a USB inter-
rupt is triggered.
The serial interface interrupt is indicating by the interrupt
flag (SIF: bit 5 of INTC1 or SI2F: bit 6 of INTC1), that is
caused by received or transferred a complete 8-bit data
between HT82A523R and external device. The serial in-
terface interrupt is controlled by setting the Serial inter-
face interrupt control bit (ESII: bit 1 of INTC1 or ESI2I:
bit2 of INTC1). After the interrupt is enabled (by setting
SBEN; bit 4 of SBCR or SBCR2), and the stack is not full
and the SIF is set, a subroutine call to location 14H or
18H occurs.
During the execution of an interrupt subroutine, other in-
terrupt acknowledge signals are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, RET or RETI
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
It is recommended that a program does not use the
rupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only one
Rev. 1.30
CALL subroutine within the interrupt subroutine. Inter-
External Interrupt
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
USB Interrupt
Serial Interface Interrupt
Serial Interface 2 Interrupt
Interrupt Source
Priority
1
2
3
4
5
6
Vector
0CH
04H
08H
10H
14H
18H
11
stack is left and enabling the interrupt is not well con-
trolled, the original control sequence will be damaged
once the CALL operates in the interrupt subroutine.
Oscillator Configuration
There is an oscillator circuit in the microcontroller.
This oscillator is designed for system clocks. The HALT
mode stops the system oscillator and ignores an exter-
nal signal to conserve power.
A crystal across OSC1 and OSC2 is needed to provide
the feedback and phase shift required for the oscillator.
No other external components are required. Instead of a
crystal, a resonator can also be connected between
OSC1 and OSC2 to get a frequency reference, but two
external capacitors in OSC1 and OSC2 are required.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters a power down mode and the system
clock is stopped, but the WDT oscillator still works. The
WDT oscillator can be disabled by ROM code option to
conserve power.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys-
tem clock divided by 4) determined by options. This
timer is designed to prevent a software malfunction or
sequence jumping to an unknown location with unpre-
dictable results. The watchdog timer can be disabled by
options. If the watchdog timer is disabled, all executions
related to the WDT results in no operation.
Once an internal WDT oscillator (RC oscillator with a pe-
riod of 65 s, normally at 5V) is selected, it is divided by
2
WDT time-out minimum period is about 300ms. This
time-out period may vary with temperature, VDD and
process variations. By selection from the WDT option,
longer time-out periods can be realized. If the WDT
time-out is selected as 2
period is divided by 2
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the
same manner except that in the HALT state the WDT
may stop counting and lose its protecting purpose. In
this situation the logic can only be restarted by external
logic. If the device operates in a noisy environment, us-
ing the on-chip RC oscillator (WDT OSC) is strongly rec-
ommended, since the HALT will stop the system clock.
12
~2
16
(by option to get the WDT time-out period). The
System Oscillator
15
which about 2.3s.
15
~2
16
, the maximum time-out
HT82A523R
May 13, 2008