ht82a523r Holtek Semiconductor Inc., ht82a523r Datasheet - Page 17

• Manufacturer Part Number: ht82a523r
• Description: Ht82a523r -- Usb 2.0 Full Speed 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

Input/Output Ports
There are 40 bidirectional input/output lines in the
microcontroller, labeled from PA to PE, which are
mapped to the data memory of [12H], [14H], [16H],
[18H] and [1A] respectively. All of these I/O ports can be
used for input and output operations. For input opera-
tion, these ports are non-latching, that is, the inputs
must be ready at the T2 rising edge of instruction MOV
A,[m] (m=12H, 14H, 16H, 18H or 1A). For output oper-
ation, all the data is latched and remains unchanged un-
til the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC, PEC) to control the input/output configura-
tion. With this control register, CMOS output or Schmitt
trigger input with or without pull-high resistor structures
can be reconfigured dynamically under software control.
To function as an input, the corresponding latch of the
control register must write a 1 . The input source also
depends on the control register. If the control register bit
is 1 the input will read the pad state. If the control reg-
ister bit is 0 the contents of the latches will move to the
internal bus. The latter is possible in the Read-mod-
ify-write instruction. For output function, CMOS is the
only configuration (except PB can be configured as
Rev. 1.30
Bit No.
2~7
0
1
CLKAUTOB
CLKEN
Label
CLKEN=1, enable CLK output. CLKEN=0, disable CLK output.
CLKAUTOB=0, CLK output is disabled when FIFO is full or CLKEN is 0.
CLKAUTOB=1, CLK output is controlled by CLKEN only.
Unused bit, read as 0
CLK (1CH) Register
Input/Output Ports
17
CMOS output or NMOS output). These control registers
are mapped to locations 13H, 15H, 17H, 19H and 1BH.
PA0 is pin-shared with PSYNC signal (dependent on
PSYNC option, the rising edge of PSYNC is used to syn-
chronize the SBDR data of the serial interface which is
pin-shared with port E).
PB0 is pin-shared with CLK signal (dependent on CLK
option).
After a chip reset, these input/output lines remain at high
levels or floating state (depending on the pull-high op-
tions). Each bit of these input/output latches can be set
or cleared by SET [m].i and CLR [m].i (m=12H, 14H,
16H, 18H or 1AH ) instructions.
Some instructions first input data and then follow the
output operations. For example, SET [m].i , CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
All the I/O ports have the capability of waking-up the device.
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
Function
HT82A523R
May 13, 2008