zl2005 Intersil Corporation, zl2005 Datasheet - Page 13

• Manufacturer Part Number: zl2005
• Description: Digital-dc? Integrated Power Management And Conversion Ic
• Manufacturer: Intersil Corporation

During time D, QH is on and V
across the inductor. The current ramps up as shown in
Figure 7.
When QH turns off (time 1-D), the current flowing in
the inductor must continue to flow from the ground up
through QL, during which the current ramps down.
Since the output capacitor C
ance at the switching frequency, the AC component of
the inductor current is filtered from the output voltage
so the load sees nearly a DC voltage.
Typically, buck converters specify a maximum duty
cycle that effectively limits the maximum output volt-
age that can be realized for a given input voltage. This
duty cycle limit ensures that the low-side MOSFET is
allowed to turn on for a minimum amount of time dur-
ing each switching cycle, which enables the bootstrap
capacitor (CB in Figure 6) to be charged up and pro-
vide adequate gate drive voltage for the high-side
MOSFET. See Section 5.2, “High-side Driver Boost
Circuit,” for more details.
In general, the size of components L1 and C
well as the overall efficiency of the circuit are
inversely proportional to the switching frequency, f
Therefore, the highest efficiency circuit may be real-
ized by switching the MOSFETs at the lowest possible
frequency; however, this will result in the largest com-
ponent size. Conversely, the smallest possible foot-
print may be realized by switching at the fastest
possible frequency but this gives a somewhat lower
efficiency. Each user should determine the optimal
combination of size and efficiency when determining
the switching frequency for each application.
The block diagram for the ZL2005 is illustrated in
Figure 5. In this circuit, the target output voltage is
regulated by connecting the VSEN pin directly to the
V
IN
– V
-V
Figure 7. Inductor Waveform
OUT
OUT
0
D
13
Time
OUT
1-D
IN
exhibits a low imped-
– V
OUT
IL
IL
I
o
is applied
pk
v
OUT
SW
as
ZL2005
.
output regulation point. The VSEN signal is then com-
pared to a reference voltage that has been set to the
desired output voltage level by the user. The error sig-
nal derived from this comparison is converted to a dig-
ital value with a low-resolution, analog to digital (A/
D) converter. The digital signal is applied to an adjust-
able digital compensation filter, and the compensated
signal is used to derive the appropriate PWM duty
cycle for driving the external MOSFETs in a way that
produces the desired output.
The ZL2005 also incorporates a non-linear response
(NLR) loop to reduce the response time and output
deviation in response to a load transient. The ZL2005
has an efficiency optimization circuit that continu-
ously monitors the power converter’s operating condi-
tions and adjusts the turn-on and turn-off timing of the
high-side and low-side MOSFETs to optimize the
overall efficiency of the power supply.
4.3 Power Management Overview
The ZL2005 incorporates a wide range of configurable
power management features that are simple to imple-
ment with no external components. Additionally, the
ZL2005 includes circuit protection features that con-
tinuously safeguard the load from damage due to
unexpected system faults. The ZL2005 can continu-
ously monitor input voltage, output voltage/current,
internal temperature, and the temperature of an exter-
nal thermal diode. A Power Good output signal is pro-
vided to enable power-on reset functionality for an
external processor.
All power management functions can be configured
using either simple pin configuration techniques (Fig-
ure 8) or via the I
parameters can be pre-configured to provide alerts for
specific conditions. See Application Note AN13 for
more details on SMBus monitoring.
4.4 Multi-mode Pins
In order to simplify circuit design, the ZL2005 incor-
porates patented multi-mode pins that allow the user to
easily configure many aspects of the device without
requiring the user to program the IC. Most power man-
agement features can be configured using these pins.
The multi-mode pins can respond to four different
connections as shown in Table 5. Any combination of
connections is allowed among the multi-mode pins.
2
C/SMBus interface. Monitoring
February 18, 2009
FN6848.0