afs600 Actel Corporation, afs600 Datasheet - Page 48

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

The Control/Status register (CTRL_STAT) is an 8-bit
register that defines the operation of the RTC. The
Control register can reset the RTC, enabling operation to
begin with all zeroes in the counter. The RTC can be
configured to clear upon a match with the Match
Table 2-17 • RTC Control/Status Register
2 -3 4
Bit
7
6
5
4:3
2
1
0
Notes:
1. Default state (set when V
2. Reset of all RTC states (except this Control/Status register) occurs asynchronously if V
3. Reset is removed synchronously after two rising edges of ACM_CLK, following both V
4. Counter will first increment on the 64th rising edge of RTCCLK after all of the following are true:
Actel Fusion Programmable System Chips
and will then increment every 128 RTCCLK cycles.
b. rstb_cnt (CTRL_STAT bit 1) is set to 1
c. cntr_en (CTRL_STAT bit 6) is set to 1
a. reset is removed
xt_mode[1:0]
rst_cnt_omat
vr_en_mat
rstb_cnt
cntr_en
xtal_en
Name
rtc_rst
CC33UP
RTC Reset: Writing a logic 1 to this bit causes an RTC reset.
synchronous deassertion of reset after two ACM_CLK cycles if V
Counter Enable: A logic 1 in this bit will enable the counter if the RTC is not in reset.
It takes 64 RTCCLK positive edges (one-half of the prescaler division factor), after reset is removed and
cntr_en = 1, before the counter is incremented.
A logic 0 in this bit resets the prescaler and therefore suspends incrementing the counter, but the
counter is not reset.
Before writing to the counter registers, the counter must be disabled.
Voltage Regulator Enable on Match: Writing a logic 1 to this bit will allow the RTCMATCH output port
to go to logic 1 when a match occurs between the 40-bit counter and the 40-bit match register.
Logic 0 forces RTCMATCH to logic 0 to prevent enabling the voltage regulator from the RTC.
Crystal Oscillator Mode: These bits control the RTCXTLMODE[1:0] output ports that are connected to
the RTCMODE[1:0] input pins of the crystal oscillator pad. For 32 kHz crystal operation, this should be
set to '01'.
(See the
Reset Counter on Match: A logic 1 written to this bit allows the counter to clear itself when a match
occurs. In this situation, the 40-bit counter clears on the next rising edge of the prescaled clock,
approximately 4 ms after the match occurs (the prescaled clock toggles at a rate of 256 Hz, given a
32.768 kHz external crystal).
A logic 0 written to this bit allows the counter to increment indefinitely while still allowing match events
to occur.
Counter Reset: A logic 0 resets the 40-bit counter value to zero. A logic 1 allows the counter to count.
Crystal Oscillator Enable: This bit controls the RTCXTLSEL output port connected to the SELMODE input
pin of the crystal oscillator. If a logic 0 is written to this bit, only the FPGA fabric can be used to control
the crystal oscillator EN and MODE[1:0] inputs.
xtal_en = 1: RTC takes control of crystal oscillator. For example, the RTC Mode bits configure the crystal
oscillator (not the FPGA mode bits).
To enable sleep mode, set xtal_en = ‘0’, so the crystal is controlled from the FPGA EN signal. Then when
the FPGA is powered down, the signal from the fpga_en will be 0. It disables the crystal oscillator.
= 0) for bits 0–7 is logic 0.
"Crystal Oscillator" section on page
A d v a n c e d v 1 . 4
register, or it can continue to count while still setting the
match signal. To enable the Fusion device to power up at
a specific time or at periodic intervals, the RTC can be
configured to turn on the 1.5 V voltage regulator.
Table 2-17
Description
2-20.)
4
details the CTRL_STAT settings.
CC33UP
CC33UP
= 0 or CTRL_STAT bit 7 (rtc_rst) is set to 1.
2
Writing a logic 0 to this bit will allow
CC33UP
= 1 and rtc_rst = 0.
= 1.
3
4