afs600 Actel Corporation, afs600 Datasheet - Page 38

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

Global Buffers with Programmable Delay
The CLKDLY macro is a pass-through clock source that
does not use the PLL, but provides the ability to delay the
clock input using a programmable delay
The CLKDLY macro takes the selected clock input and
adds a user-defined delay element. This macro generates
an output clock phase shift from the input clock.
The CLKDLY macro can be driven by an INBUF macro to
create a composite macro, where the I/O macro drives
the global buffer (with programmable delay) using a
hardwired connection. In this case, the I/O must be
placed in one of the dedicated global I/O locations.
Many specific INBUF macros support the wide variety of
single-ended and differential I/O standards supported by
the Fusion family. The available INBUF macros are
described in the
Library Guide.
Figure 2-21 • Fusion CCC Options: Global Buffers with Programmable Delay
2 -2 4
Actel Fusion Programmable System Chips
PADN
PADP
Fusion, IGLOO/e and ProASIC3/E Macro
Input LVDS/LVPECL Macro
PAD
Clock Source
INBUF* Macro
Y
Y
(Figure
2-21).
A d v a n c e d v 1 . 4
CLK
DLYGL[4:0]
Clock Conditioning
The CLKDLY macro can be driven directly from the FPGA
core.
The CLKDLY macro can also be driven from an I/O that is
routed through the FPGA regular routing fabric. In this
case, users must instantiate a special macro, PLLINT, to
differentiate
described earlier.
The visual CLKDLY configuration in the SmartGen part of
the Libero IDE and Designer tools allows the user to
select the desired amount of delay and configures the
delay elements appropriately. SmartGen also allows the
user to select the input clock source. SmartGen will
automatically instantiate the special macro, PLLINT,
when needed.
from
GL
the
hardwired
Output
GLA
or
GLB
or
GLC
I/O
connection