afs600 Actel Corporation, afs600 Datasheet - Page 218

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

V
V
V
V
Fusion devices have a separate bank for the dedicated
JTAG pins. The JTAG pins can be run at any voltage from
1.5 V to 3.3 V (nominal). Isolating the JTAG power supply
in a separate I/O bank gives greater flexibility in supply
selection and simplifies power supply and PCB design. If
the JTAG interface is neither used nor planned to be
used, the V
tied to GND. It should be noted that V
powered for JTAG operation; V
If a Fusion device is in a JTAG chain of interconnected
boards and it is desired to power down the board
containing the Fusion device, this may be done provided
both V
otherwise, JTAG signals will not be able to transition the
Fusion device, even in bypass mode.
V
Fusion devices support single-voltage ISP programming
of
programming, V
During normal device operation, V
floating or can be tied to any voltage between 0 V and
3.6 V.
When the V
charge pump circuitry, resulting in no sources of
oscillation from the charge pump circuitry.
For proper programming, 0.01 µF and 0.33 µF capacitors
(both rated at 16 V) are to be connected in parallel
across V
FPGA pins as possible.
User-Defined Supply Pins
V
Reference voltage for I/O minibanks. Both AFS600 and
AFS1500 (north bank only) support Actel Pro I/O. These I/
O banks support voltage reference standard I/O. The V
pins are configured by the user from regular I/Os, and any
I/O in a bank, except JTAG I/Os, can be designated as the
voltage reference I/O. Only certain I/O standards require a
voltage reference—HSTL (I) and (II), SSTL2 (I) and (II),
SSTL3 (I) and (II), and GTL/GTL+. One V
the number of I/Os available in its minibank.
VAREF
The Fusion device can be configured to generate a 2.56 V
internal reference voltage that can be used by the ADC.
2 -2 0 4
COMPLA/B
COMPLA
COMPLB
JTAG
PUMP
REF
Actel Fusion Programmable System Chips
2. The ADC is functional with an external reference down to 1 V; however to meet the performance parameters highlighted in
the
the datasheet, refer to the VAREF specification in
JTAG
PUMP
is the ground of the east PLL (CCC location C).
is the ground of the west PLL (CCC location F) and
configuration
JTAG
and V
PUMP
and GND, and positioned as close to the
pin together with the TRST pin could be
PUMP
CC
pin is tied to ground, it shuts off the
Ground for West and East PLL
JTAG Supply Voltage
Programming Supply Voltage
I/O Voltage Reference
Analog Reference Voltage
to the Fusion part remain powered;
should be in the 3.3 V +/-5% range.
flash
JTAG
and
alone is insufficient.
CC
REF
PUMP
is required to be
FlashROM.
pin can support
can be left
Table 3-2 on page
A d v a n c e d v 1 . 4
For
REF
While using the internal reference, the reference voltage
is output on the VAREF pin for use as a system reference.
If a different reference voltage is required, it can be
supplied by an external source and applied to this pin.
The valid range of values that can be supplied to the
ADC is 1.0 V to 3.3 V. When VAREF is internally generated
by the Fusion device, a bypass capacitor must be
connected from this pin to ground. The value of the
bypass capacitor should be between 3.3 µF and 22 µF,
which is based on the needs of the individual designs.
The choice of the capacitor value has an impact on the
settling time it takes the VAREF signal to reach the
required specification of 2.56 V to initiate valid
conversions by the ADC. If the lower capacitor value is
chosen, the settling time required for VAREF to achieve
2.56 V will be shorter than when selecting the larger
capacitor value. The above range of capacitor values
supports the accuracy specification of the ADC, which is
detailed in the datasheet. Designers choosing the smaller
capacitor value will not obtain as much margin in the
accuracy as that achieved with a larger capacitor value.
Depending on the capacitor value selected in the Analog
System Builder, a tool in Libero IDE, an automatic delay
circuit will be generated using logic tiles available within
the FPGA to ensure that VAREF has achieved the 2.56 V
value. Actel recommends customers use 10 uF as the
value of the bypass capacitor. Designers choosing to use
an external VAREF need to ensure that a stable and clean
VAREF source is supplied to the VAREF pin before
initiating conversions by the ADC. Designers should also
make sure that the ADCRESET signal is deasserted before
initiating valid conversions.
User Pins
I/O
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Input and output signal levels are
compatible with the I/O standard selected. Unused I/O
pins are configured as inputs with pull-up resistors.
During programming, I/Os become tristated and weakly
pulled up to V
continuously powered up, when the device transitions
from programming to operating mode, the I/Os get
instantly configured to the desired user configuration.
Axy
Analog I/O pin, where x is the analog pad type
(C = current pad, G = Gate driver pad, T = Temperature
pad, V = Voltage pad) and y is the Analog Quad number
(0 to 9). There is a minimum 1 MΩ to ground on AV, AC,
and AT. This pin can be left floating when it is unused.
3-3.
CCI
User Input/Output
Analog Input/Output
. With the V
2
CCI
and V
CC
supplies