wm8802scft/v Wolfgang Knap, wm8802scft/v Datasheet - Page 52

• Manufacturer Part Number: wm8802scft/v
• Description: Digital Audio Interface Transceiver
• Manufacturer: Wolfgang Knap

WM8802
Table 18 Relation between Input Data Length Setting Register and Data Length
w
Command address: 11
DI6
REGISTER ADDRESS
CCB address: 0xE8;
0
0
0
0
DI5
0
0
1
1
DI4
0
1
0
1
Digital audio input/output setting:
CHANNEL STATUS DATA WRITE
CCB address is set to 0xE9 for channel status data write in the modulation function.
DI0 to DI7 are not channel status bits. Always input a chip address to DI0 and DI1. Input "0" to DI2,
DI3 and DI7 because they are reserved for the system. Select the channel status data write length
with DI4 to DI6. Up to 48 bits can be set, in 8-bit units.
After CE becomes Low, input data is written from preamble B.
TXDFS
TXLRP
TDTSEL
TXMUT
TXMOD [1:0]
Bit 0 to bit 7
Bit 0 to bit 15
Bit 0 to bit 23
Bit 0 to bit 31
DI15
DI7
1
0
INPUT TABLE DATA
RANGE
DI14
DI6
0
0
TXMOD1
TDATA input data format setting
0: I
1: MSB-first front-loading data input
TLRCK input clock polarity setting
0: Low period: L-channel data; High period: R-channel data (initial
value)
1: Low period: R-channel data; High period: L-channel data
Input data setting
0: TDATA input data (initial value)
1: SDIN input data
TXO output setting
0: Conversion data output (initial value)
1: Low fixed output
Mode setting
00: Normal operation (L-channel, R-channel stereo mode) (initial value)
01: L-channel continuous (time-division mode)
10: R-channel continuous (time-division mode)
11: reserved
DI13
DI5
2
1
S data input (initial value)
TXMOD0
DI12
DI4
1
DI6
1
1
1
1
TXMUT
DI11
DI3
DI5
0
0
0
1
1
TDTSEL
DI4
DI10
0
1
0
1
DI2
0
Bit 0 to bit 39
Bit 0 to bit 47
Reserved
Reserved
INPUT TABLE DATA
TXLRP
PP Rev 1.1 April 2004
CAU
DI1
DI9
RANGE
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TXDFS
CAL
DI0
DI8
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