wm8802scft/v Wolfgang Knap, wm8802scft/v Datasheet - Page 15

• Manufacturer Part Number: wm8802scft/v
• Description: Digital Audio Interface Transceiver
• Manufacturer: Wolfgang Knap

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The oscillation amplifier can be stopped if it is unnecessary. When operation is resumed it is
recommended to return to the normal operation after an interval of 10ms or longer to allow the
resonator oscillation to stabilise.
XMCK outputs the XIN clock. The XMCK output settings are performed with XMSEL[0:1]. The XIN
clock can be set to 1/1, 1/2 or muted output.
No clock is needed for XIN when only using the modulation function. In this case, the built-in
oscillation amplifier and frequency divider are used for RMCK, RBCK, and RLRCK clock generation.
Input the crystal resonator frequency across XIN and XOUT (if using only the oscillation amplifier) or
an external clock to XIN. The potential of digital data input pins RX0 to RX6 should be fixed. The DIR
function is stopped using RXOPR and PLLOPR and should not be set at this time. The output clock
may also be muted.
MASTER CLOCK AND CLOCK SOURCE SWITCHING
The RMCK, RBCK, and RLRCK, and the SBCK and SLRCK (see below) clock sources can be
selected from the following three master clocks.
(1)
(2)
(3)
Clock source switching can be done in one of two ways, either by setting the R system and the S
system on an interconnected basis or fixing the S system to the XIN source and setting only the R
system. This setting is performed using SELMTD, OCKSEL and RCKSEL.
The clock source is automatically switched between PLL clock and XIN clock by locking/unlocking
the PLL. The continuity of the clock is maintained at this time. However, if switching the clock source
with SELMTD, the continuity of the S system is not maintained.
The clock source can be switched to XIN using OCKSEL and RCKSEL, regardless of the PLL status.
The clock source switch command and clock output of the R and S systems are shown below.
Table 7 Correspondence between Clock Source Switch Commands and Clock Output Pins
Table 8 Relationship between Clock Source Switch Commands and
The TMCK source is selected using EXSYNC. This setting results in the same operation as when
256fs is set with the PLL source (i.e. PLLSEL set to 256fs).
The various clocks are output with the TMCK source as the master clock and the PLL clock status is
output if data synchronised with TMCK is input. The XIN source is switched with OCKSEL and
RCKSEL. When the TMCK source is not supplied or the input data is not synchronized, the source is
switched to the XIN source; this is similar to the PLL source unlocked status.
The PLL status can always be monitored with RERR even after the XIN source is switched. The
processed information can also be read with the micro-controller interface regardless of the PLL
status.
SELMTD
0
1
SELMTD
Clock Sources when PLL Locked/Unlocked
PLL source
XIN source
TMCK source
0
1
OCKSEL
X
X
0
1
RCKSEL
(256fs or 512fs)
(12.288MHz or 24.576MHz)
(256fs)
R SYSTEM OUTPUT CLOCK
X
X
0
1
According to OCKSEL
According to RCKSEL
Locked
PLL
PLL
R SYSTEM CLOCK
XIN
XIN
SOURCE
Unlocked
XIN
XIN
XIN
XIN
S SYSTEM OUTPUT CLOCK
According to OCKSEL
Fixed to XIN source
Locked
S SYSTEM CLOCK
PLL
XIN
XIN
XIN
PP Rev 1.1 April 2004
SOURCE
WM8802
Unlocked
XIN
XIN
XIN
XIN
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