wm8802scft/v Wolfgang Knap, wm8802scft/v Datasheet - Page 20

• Manufacturer Part Number: wm8802scft/v
• Description: Digital Audio Interface Transceiver
• Manufacturer: Wolfgang Knap

WM8802
Figure 8 Clock Switch Timing
w
Locked status
Locked status
XTAL Clock
XTAL Clock
RX0 to RX6
RX0 to RX6
VCO Clock
VCO Clock
RMCK
RMCK
RERR
CKST
RERR
CKST
Digital Data
CLOCK SWITCH TRANSITION SIGNAL OUTPUT ( CKST )
In the lock-in stage (PLL locked following the detection of input data) the CKST Low pulse falls at
the word clock edge generated from the XIN clock. The CKST Low pulse rises at the same timing as
RERR following the lapse of a given period.
In the unlock stage, the CKST Low pulse falls at the same timing as the PLL lock detection signal
RERR and rises following a given number of word clocks generated from the XIN clock.
The PLL lock status change and clock change timing is detected by the rising and falling edges of
the CKST Low pulse.
CKST outputs Low when the output clock changes during PLL lock/unlock.
Unlock
Lock
(a) Lock-in stage
(b) Unlock stage
Digital Data
After PLL lock
Same timing as RERR
Lock
Unlock
45 ms to 300 ms
0.6 ms to 6.4 ms
Same timing as
RERR
PP Rev 1.1 April 2004
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