wm8802scft/v Wolfgang Knap, wm8802scft/v Datasheet - Page 44

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wm8802scft/v

Manufacturer Part Number
wm8802scft/v
Description
Digital Audio Interface Transceiver
Manufacturer
Wolfgang Knap
Datasheet
WM8802
w
REGISTER ADDRESS
Command address: 3
CCB address: 0xE8;
R system output clock setting:
3.072MHz is output from RBCK if the RMCK frequency is set lower than RBCK when the XIN source
is used.
XRLRCK1 XRLRCK0
PRSEL [1:0]
XRSEL [1:0]
XRBCK [1:0]
XRLRCK [1:0]
DI15
DI7
0
DI14
DI6
0
XRBCK1
RMCK output frequency setting during PLL lock
00: 1/2 of PLLSEL setting frequency (initial value)
01: 1/1 of PLLSEL setting frequency
10: 1/4 of PLLSEL setting frequency
11: Muted
RMCK output frequency setting during XIN source
00: 1/1 of XINSEL setting frequency (initial value)
01: 1/2 of XINSEL setting frequency
10: 1/4 of XINSEL setting frequency
11: Muted
RBCK output frequency setting during XIN source
00: 3.072MHz output (initial value)
01: 6.144MHz output
10: 12.288MHz output
11: Muted
RLRCK output frequency setting during XIN source
00: 48kHz output (initial value)
01: 96kHz output
10: 192kHz output
11: Muted
DI13
DI5
1
XRBCK0
DI12
DI4
1
XRSEL1
DI11
DI3
0
XRSEL0
DI10
DI2
0
PRSEL1
PP Rev 1.1 April 2004
CAU
DI1
DI9
Product Preview
PRSEL0
CAL
DI0
DI8
44

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