wm8351 Wolfson Microelectronics plc, wm8351 Datasheet - Page 214

• Manufacturer Part Number: wm8351
• Description: Wolfson Audioplus? Stereo Codec With Power Management
• Manufacturer: Wolfson Microelectronics plc

WM8351
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R154 (9Ah) AUX3 Readback
R155 (9Bh) AUX4 Readback
R156 (9Ch) USB Voltage Readback
R157 (9Dh) LINE Voltage Readback
R158 (9Eh) BATT Voltage Readback
R163 (A3h) Generic Comparator
R164 (A4h) Generic comparator 1
R165 (A5h) Generic comparator 2
R166 (A6h) Generic comparator 3
R167 (A7h) Generic comparator 4
R168 (A8h) Battery Charger Control 1
R169 (A9h) Battery Charger Control 2
R170 (AAh) Battery Charger Control 3
R172 (ACh) Current Sink Driver A
R173 (ADh) CSA Flash control
R176 (B0h) DCDC/LDO requested
R144 (90h) Digitiser Control (1)
R145 (91h) Digitiser Control (2)
R152 (98h) AUX1 Readback
R153 (99h) AUX2 Readback
R159 (9Fh) Chip Temp Readback
REG
Control
NAME
AUXADC_E
CHG_ACTI
CHG_ENA
CS1_FLAS
CS1_ENA
H_MODE
LS_ENA
VE (M)
NA (s)
(KMs)
(Ms)
15
(s)
(s)
0
0
0
0
0
0
0
0
0
0
0
DCMP1_SRCSEL[2:0] (s)
DCMP2_SRCSEL[2:0] (s)
DCMP3_SRCSEL[2:0] (s)
DCMP4_SRCSEL[2:0] (s)
CS1_TRIGS
AUXADC_C
CHG_PAUS
AUXADC_SCALE1[1:0] AUXADC_R
AUXADC_SCALE2[1:0] AUXADC_R
AUXADC_SCALE3[1:0] AUXADC_R
AUXADC_SCALE4[1:0] AUXADC_R
RC (s)
TC (s)
E (s)
14
0
0
0
0
0
0
0
0
0
0
AUXADC_MASKMODE[1:
CS1_DRIVE
AUXADC_P
OLL (s)
(Ms)
13
0
0
0
0
0
0
CHG_STS[1:0]
0
0
0
0] (s)
CS1_HIB_M
AUXADC_H
DCMP1_GT
DCMP2_GT
DCMP3_GT
DCMP4_GT
H_RATE (s)
CS1_FLAS
IB_MODE
ODE (s)
12
EF1
EF2
EF3
EF4
(s)
0
0
0
0
0
0
0
CHG_EOC_SEL[2:0] (K)
LDO4_ENA
(Ms)
11
0
0
0
0
0
0
LDO3_ENA
CHG_TIME[3:0] (KM)
10
(Ms)
0
0
0
0
0
AUXADC_CRATE[2:0] (s)
CS1_FLASH_DUR[1:0] (s)
KLE_TEMP
CHG_TRIC
LDO2_ENA
_CHOKE
(Ks)
(Ms)
9
0
0
0
0
LDO1_ENA
CHG_TRIC
KLE_USB_
CHOKE
(Ms)
(Ks)
8
0
0
0
0
AUXADC_S
CHG_RECO
CHG_MASK
VER_T (Ks)
_WALL_FB
CHG_FRC
EL8 (s)
(Ks)
(Ks)
7
0
0
0
0
0
AUXADC_DATA_CHIPTEMP[11:0]
AUXADC_DATA_BATT[11:0]
AUXADC_DATA_USB[11:0]
AUXADC_DATA_LINE[11:0]
AUXADC_S
CHG_END_
CHG_TRIC
CHG_THROTTLE_T[1:0]
AUXADC_DATA1[11:0]
AUXADC_DATA2[11:0]
AUXADC_DATA3[11:0]
AUXADC_DATA4[11:0]
KLE_SEL
ACT (Ks)
EL7 (s)
DCMP1_THR[11:0]
DCMP2_THR[11:0]
DCMP3_THR[11:0]
DCMP4_THR[11:0]
6
(K)
0
0
0
0
0
(K)
AUXADC_S
CHG_FAST
CS1_OFF_RAMP[1:0] (s)
EL6 (s)
(KMs)
CHG_VSEL[1:0] (K)
5
0
0
0
AUXADC_S
CHG_FAST
_USB_THR
OTTLE (Ks)
EL5 (s)
4
0
0
0
0
AUXADC_S
DCMP4_EN
CHG_NTC_
DC4_ENA
MON (M)
EL4 (s)
A (s)
(Ms)
CS1_ISEL[5:0] (s)
3
0
0
0
AUXADC_S
AUXADC_C
DCMP3_EN
_HOT_MON
CHG_BATT
DC3_ENA
EL3 (s)
AL (s)
A (s)
CHG_ISEL[3:0] (K)
(Ms)
(M)
2
0
0
AUXADC_S
AUXADC_R
DCMP2_EN
CHG_BATT
_COLD_MO
BMODE (s)
CS1_ON_RAMP[1:0] (s)
DC2_ENA
EL2 (s)
N (M)
A (s)
(Ms)
1
0
PD, June 2009, Rev 4.1
AUXADC_S
DCMP1_EN
_TEMP_MO
CHG_CHIP
AUXADC_
DC1_ENA
WAIT (s)
EL1 (s)
N (KM)
A (s)
(Ms)
0
Production Data
0
DEFAULT
A00Fh
0B06h
0000h
0002h
7000h
7000h
7000h
7000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
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