wm8351 Wolfson Microelectronics plc, wm8351 Datasheet - Page 199

• Manufacturer Part Number: wm8351
• Description: Wolfson Audioplus? Stereo Codec With Power Management
• Manufacturer: Wolfson Microelectronics plc

Production Data
24.1 CONFIGURING THE IRQ PIN
24.2 FIRST LEVEL INTERRUPTS
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The default polarity of IRQ is active low; this can be changed to active high if desired, by writing to
the IRQ_POL bit.
When the WM8351 is in the HIBERNATE state, interrupts can be disabled or can remain active. The
desired behaviour can be selected using the IRQ_HIB_MODE bit.
R3 (03h)
System
Control 1
R5 (05h)
System
Hibernate
Table 140 Interrupts in HIBERNATE State
Each first level interrupt has a status bit in Register R24, which can be read to determine the origin of
an IRQ event. Each of these bits may be masked by setting the corresponding field in Register R32.
R24 (18h)
System
Interrupts
R32 (20h)
System
Interrupt Mask
Note: Register is R24 is read-only.
Table 141 First Level Interrupt Status and Mask Bits
ADDRESS
ADDRESS
13:0
BIT
BIT
13
12
0
3
9
8
7
6
5
4
3
2
1
0
IRQ_POL
IRQ_HIB_MOD
E
OC_INT
UV_INT
CS_INT
EXT_INT
CODEC_INT
GP_INT
AUXADC_INT
RTC_INT
SYS_INT
CHG_INT
USB_INT
WKUP_INT
“IM_” + name of respective
bit in R25
LABEL
LABEL
DEFAULT
0
0
First-level over-current interrupt.
Note: This bit is cleared once read.
First-level under-voltage interrupt.
Note: This bit is cleared once read.
First-level current sink interrupt.
Note: This bit is cleared once read.
First-level external interrupt.
Note: This bit is cleared once read.
First-level codec interrupt.
Note: This bit is cleared once read.
First-level GPIO interrupt.
Note: This bit is cleared once read.
First-level AUXADC comparator interrupt.
Note: This bit is cleared once read.
First-level RTC interrupt.
Note: This bit is cleared once read.
First-level system interrupt.
Note: This bit is cleared once read.
First-level charger interrupt.
Note: This bit is cleared once read.
First-level USB interrupt.
Note: This bit is cleared once read.
First-level wakeup interrupt.
Note: This bit is cleared once read.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Each bit in R32 enables or masks the
corresponding bit in R24.
The default value for these bits is 1
(masked)
IRQ pin polarity
0 = active low (/IRQ)
1 = active high (IRQ)
IRQ pin state in hibernate mode
0 = Normal operation
1 = Forced to indicate there is no IRQ.
DESCRIPTION
DESCRIPTION
PD, June 2009, Rev 4.1
WM8351
199