wm9714l Wolfson Microelectronics plc, wm9714l Datasheet - Page 79

• Manufacturer Part Number: wm9714l
• Description: Ac?97 Audio Codec
• Manufacturer: Wolfson Microelectronics plc

Pre-Production
ADDITIONAL POWER MANAGEMENT
POWER ON RESET (POR)
w
Mixer output inverters: see “Mixer output Inverters” section. Inverters are disabled by default.
SLEEP MODE
Whenever the PR4 bit (reg. 26h) is set, the AC-Link interface is disabled, and the WM9714L is in
sleep mode. There is in fact a very large number of different sleep modes, depending on the other
control bits. For example, the low-power standby mode described below is a sleep mode. It is
desirable to use sleep modes whenever possible, as this will save power. The following functions do
not require a clock and can therefore operate in sleep mode:
The WM9714L can awake from sleep mode as a result of
LOW POWER STANDBY MODE
If all the bits in registers 26h, 3Ch and 3Eh are set except VMID1M (register 3Ch, bit 14), then the
WM9714L is in low-power standby mode and consumes very little current. A 1MΩ resistor string
remains connected across AVDD to generate VREF. This is necessary if the on-chip analogue
comparators are used (see “Battery Alarm and Battery Measurement” section), and helps shorten the
delay between wake-up and playback readiness. If VREF is not required, the 1MΩ resistor string can
be disabled by setting the VMID1M bit, reducing current consumption further.
SAVING POWER AT LOW SUPPLY VOLTAGES
The analogue supplies to the WM9714L can run from 1.8V to 3.6V. By default, all analogue circuitry
on the IC is optimized to run at 3.3V. This set-up is also good for all other supply voltages down to
1.8V. However, at lower voltages, it is possible to save power by reducing the internal bias currents
used in the analogue circuitry. This is controlled as shown below.
Table 62 Analogue Bias Selection
The WM9714L has an internal power on reset (PORB) which ensures that a reset is applied to all
registers until a supply threshold has been exceeded. The POR circuitry monitors the voltage for both
AVDD and DCVDD and will release the internal reset signal once these supplies are both nominally
greater than 1.36V. The internal reset signal is an AND of the PORB and RESETB input signal.
It is recommended that for operation of the WM9714L, all device power rails should be stable before
configuring the device for operation.
5Ch
REGISTER
ADDRESS
•
•
•
•
•
•
Analogue-to-analogue audio (DACs and ADCs unused), e.g. phone call mode
GPIO and interrupts
Battery alarm / analogue comparators
A warm reset on the AC-Link (according to the AC’97 specification)
A signal on a GPIO pin (if the pin is configured as an input, with wake-up enabled –
see “GPIO and Interrupt Control” section)
A virtual GPIO event such as battery alarm, etc. (see “GPIO and Interrupt Control”
section)
6:5
BIT
VBIAS
LABEL
00
DEFAULT
Analogue Bias Optimization Control
0X = Default bias current, optimized for 3.3V
10 = Low bias current, optimized for 2.5V
11 = Lowest bias current, optimized for 1.8V
DESCRIPTION
PP, Rev 3.2, October 2008
WM9714L
79