wm9714l Wolfson Microelectronics plc, wm9714l Datasheet - Page 102

• Manufacturer Part Number: wm9714l
• Description: Ac?97 Audio Codec
• Manufacturer: Wolfson Microelectronics plc

46h
WM9714L
Register 46h controls PLL clock generation.
w
REGISTER
ADDRESS
15:12
11
10
9
8
6:4
3:0
BIT
N[3:0]
LF
SDM
DIVSEL
DIVCTL
PGADDR
PGDATA
LABEL
0000 (div by 1)
0 (normal)
0 (disabled)
0 (div by 1)
0
000
0000
DEFAULT
PLL N Divide Control
0000 = Divide by 1
0001 = Divide by 1
0010 = Divide by 2
…
1111 = Divide by 15
PLL Low Frequency Input Control
1 = Low frequency mode (input clock < 8.192MHz)
0 = Normal mode
PLL SDM Enable Control
1 = Enable SDM (required for fractional N mode)
0 = Disable SDM
PLL Input Clock Division Control
0 = Divide by 1
1 = Divide according to DIVCTL
PLL Input Clock Division Value Control
0 = Divide by 2
1 = Divide by 4
Pager Address
Pager address bits to access programming of
K[21:0] and S
Pager Data
Pager data bits
PLL
[6:0]
DESCRIPTION
PP, Rev 3.2, October 2008
Pre-Production
Analogue
Audio
Outputs,
Power-Up
REFER TO
102