wm8595 Wolfson Microelectronics plc, wm8595 Datasheet - Page 18

• Manufacturer Part Number: wm8595
• Description: 24-bit 192khz 2vrms Multi-channel Codec
• Manufacturer: Wolfson Microelectronics plc

WM8595
CONTROL INTERFACE
2-WIRE (SM-BUS COMPATIBLE) SERIAL CONTROL INTERFACE MODE
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Control of the WM8595 is achieved by a 2-wire SM-bus-compliant or 3-wire SPI compliant serial
interface with readback. Software interface mode is selected using the CIFMODE pin as shown in
Table 8 below:
Table 8 Control Interface Mode Selection
Many devices can be controlled by the same bus, and each device has a unique 7-bit address.
REGISTER WRITE
The controller indicates the start of data transfer with a high to low transition on SDA while SCLK
remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus
respond to the start condition and shift in the next eight bits on SDA (7-bit address and read/write bit,
MSB first). If the device address received matches the address of the WM8595, the WM8595
responds by pulling SDA low on the next clock pulse (ACK). If the address is not recognised, the
WM8595 returns to the idle condition and waits for a new start condition with valid address.
When the WM8595 has acknowledged a correct address, the controller sends the first byte of control
data (B23 to B16, i.e. the WM8595 register address). The WM8595 then acknowledges the first data
byte by pulling SDA low for one SCLK pulse. The controller then sends a second byte of control data
(B15 to B8, i.e. the first 8 bits of register data), and the WM8595 acknowledges again by pulling SDA
low for one SCLK pulse. Finally, the controller sends a third byte of control data (B7 to B0, i.e. the
final 8 bits of register data), and the WM8595 acknowledges again by pulling SDA low for one SCLK
pulse.
The transfer of data is complete when there is a low to high transition on SDA while SCLK is high.
After receiving a complete address and data sequence the WM8595 returns to the idle state and
waits for another start condition. If a start or stop condition is detected out of sequence at any point
during data transfer (i.e. SDA changes while SCLK is high), the WM8595 reverts to the idle condition.
The WM8595 device 2-wire write address is 34h (0110100) or 36h (0110110), selectable by control
of CS
Table 9 2-Wire Control Interface Bus Address Selection
Figure 7 2-Wire Write Protocol
CIFMODE (PIN 44)
¯ ¯ .
CS
¯ ¯ (PIN 46)
High
Low
0
1
INTERFACE FORMAT
2-WIRE BUS ADDRESS (B[7:1])
2 wire
3 wire
34h (011010)
36h (011011)
PD, Rev 4.1, April 2010
Production Data
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