wm8941 Wolfson Microelectronics plc, wm8941 Datasheet - Page 84

• Manufacturer Part Number: wm8941
• Description: Mono Codec With Speaker Driver And Video Buffer
• Manufacturer: Wolfson Microelectronics plc

WM8941
w
37 (25h)
38 (26h)
39 (27h)
40 (28h)
41 (29h)
42 (2Ah)
43 (2Bh)
44 (2Ch)
REGISTER
ADDRESS
3:0
15:6
5:0
15:9
8:0
15:9
8:0
15:5
4
3
2
1
0
15:0
15:2
1
0
15:0
15:9
8
7:4
3
2
1
BIT
PLLN[3:0]
PLLK[23:18]
PLLK[17:9]
PLLK[8:0]
QBOOST
VBGAIN
VBDISOFF
VBPULLDWN
VBCLAMPEN
ALCZC
MBVSEL
AUXMODE
AUX2INPPGA
MICN2INPPGA
LABEL
1100
000h
001100
00h
010010011
00h
011101001
000h
0
0
0
0
0
0000h
0
0 (zero
cross off)
0
0000h
00h
0
0h
0
0
1
DEFAULT
Integer (N) part of PLL input/output frequency ratio.
Use values greater than 5 and less than 13.
Reserved
Fractional (K) part of PLL1 input/output frequency ratio
(treat as one 24-digit binary number).
Reserved
Fractional (K) part of PLL1 input/output frequency ratio
(treat as one 24-digit binary number).
Reserved
Fractional (K) part of PLL1 input/output frequency ratio
(treat as one 24-digit binary number).
Reserved
Video buffer gain
0 = 0dB (=6dB unloaded)
1 = +6dB (=12dB unloaded)
Disable Video Buffer DC Offset
0 = Video buffer drives down to 40mV above ground
1 = Video buffer drives to ground (not recommended)
Video buffer pull down
0 = Disabled
1 = Enabled
Reserved
Reserved
ALC uses zero cross detection circuit.
0 = Disabled (recommended)
1 = Enabled
Reserved
Reserved
Reserved
Microphone Bias Voltage Control
0 = 0.9 * AVDD
1 = 0.75 * AVDD
Reserved
Auxiliary Input Mode
0 = inverting buffer
1 = mixer (on-chip input resistor bypassed)
Select AUX amplifier output as input PGA signal
source.
0=AUX not connected to input PGA
1=AUX connected to input PGA amplifier negative
terminal.
Connect MICN to input PGA negative terminal.
0=MICN not connected to input PGA
1=MICN connected to input PGA amplifier negative
terminal.
Increases the filters Q.
Video buffer clamp enable
DESCRIPTION
PD, Rev 4.0, August 2008
Master Clock and
Phase Locked
Loop (PLL)
Master Clock and
Phase Locked
Loop (PLL)
Master Clock and
Phase Locked
Loop (PLL)
Master Clock and
Phase Locked
Loop (PLL)
Video Buffer
Video Buffer
Video Buffer
Video Buffer
ALC Control 4
Input Signal Path
Input Signal Path
Input Signal Path
Input Signal Path
Video Buffer
REFER TO
Production Data
84