wm8941 Wolfson Microelectronics plc, wm8941 Datasheet - Page 76

• Manufacturer Part Number: wm8941
• Description: Mono Codec With Speaker Driver And Video Buffer
• Manufacturer: Wolfson Microelectronics plc

WM8941
Notes:
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REGISTER BITS BY ADDRESS
1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits).
2. Register bits marked as "Reserved" should not be changed from the default.
0 (00h)
1 (01h)
2 (02h)
REGISTER
ADDRESS
[15:0] RESET /
15:9
8
7
6
5
4
3
2:0
2
1:0
15:5
4
3
2
1
0
BIT
CHIP_ID
VMID_OP_EN
LVLSHIFT_EN
AUXEN
PLLEN
MICBEN
BIASEN
DEVICE_REVIS
ION
BUFIOEN
VMIDSEL
BOOSTEN
INPPGAEN
ADCEN
LABEL
N/A
00h
0
0
0
0
0
0
000
0
00
000h
0
0
0
0
0
DEFAULT
Writing to this register will apply a software reset.
Reading from this register will return the device id
Reserved
Enables the non-VMID derived bias current generator
without enabling the VMID buffer. This bit must be set
to 1 if output amplifiers are to be enabled before VMID
is active. Once VMID and VMID buffer are enabled this
bit can be left set to 0 or left set to 1.
Enable bit for the level shifters. 1 for normal operation,
0 for standby.
Auxilliary input buffer enable
0 = OFF
1 = ON
PLL enable
0=PLL off
1=PLL on
Microphone Bias Enable
0 = OFF (high impedance output)
1 = ON
Analogue amplifier bias control
0=Disabled
1=Enabled
Readback from this register will return the device
revision in this position
Enable bit for the VMID buffer. The VMID buffer is
used to maintain a buffered VMID voltage on all
analogue input and output pins. 1. for normal operation
0. for standby (where inputs and outputs settle to
GND).
Reference string impedance to VMID pin:
00=off (open circuit)
01=50kΩ
10=250kΩ
11=5kΩ
Reserved
Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
Reserved
0 = disabled
1 = enabled
Reserved
ADC Enable Control
0 = ADC disabled
1 = ADC enabled
Input microphone PGA enable
DESCRIPTION
PD, Rev 4.0, August 2008
Resetting the
Chip /
Control Interface
Power
Management
Power
Management
Auxiliary Inputs
Master Clock and
Phase Locked
Loop (PLL)
Microphone
Biasing Circuit
Power
Management
Control Interface
Enabling the
Outputs
Power
Management
Input Boost
Input Signal Path
Analogue to
Digital Converter
(ADC)
REFER TO
Production Data
76