pt7a6527 Pericom Technology Inc, pt7a6527 Datasheet - Page 22

• Manufacturer Part Number: pt7a6527
• Description: Hdlc Controller
• Manufacturer: Pericom Technology Inc

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Table 9 Initialization of HDLC Channels (channel-per-channel)
Interrupt Structure
Special events are reported to the processor by an interrupt
logic in the PT7A6527. This logic allows the connection of
more than one PT7A6527 to one interrupt input of a
microcontroller.
The interrupt structure of the PT7A6527 is depicted in figure
20. Each HDLC channel of the circuit has its own Interrupt
Status Register (ISTA) where up to five possible interrupt
causes may be read directly. When an interrupt occurs in one
of the HDLC channels, the corresponding bit is set in the
ISTA register and the interrupt line (INT) is activated.
Simultaneously, a bit in the Vectored Interrupt Status Register
(VISR) is set which indicates which of the four HDLC
channels initiated the interrupt. Thus, to determine the cause
of an interrupt, the microcontroller performs successively a
read of the VISR register (address 36/3F) and a read of that
ISTA register which was indicated by the contents of VISR.
A read of the ISTA clears the register and deactivates the INT
line.
The position which the four bits of the Vectored Interrupt
Status Register occupy on the AD7-0 bus when the register is
read, is programmable via the Vectored Interrupt Selection bit
VIS (CCR register). Thus, when VIS = 0, the VISR bits are
read on AD bit positions 0-3, and when VIS = 1, VISR bits are
read on AD bit positions 4-7. Unoccupied bit positions on the
bus remain in a high impedance state.
The bits in VISR can be selectively masked by setting the
corresponding bits in the Vectored Interrupt Status Mask
(VISM) register to prevent one or several controllers from
generating an interrupt. In that case, interrupts remain
internally stored (pending) but are not displayed in the VISR
or ISTA registers. Further, ISTA interrupts pertaining to a
Figure 20 Interrupt Structure of the PT7A6527
PT0080(02/09)
HDLC Controller
Serial interface
Function
Mask ISM.ISTA
Register
MODE
MODE
TSR
Int. Status A
CMS1-0
CCS1-0
TSR7-0
CAC
RAC
TLP
Bits
ITF
Mask VISM. VISR
Collision mode
Channel capacity
Time slot
Inter-frame time fill pattern
Test loop
Active channel (enable receiver + transmitter, enable data outputs)
Activate HDLC receiver
Int. Status B
22
particular channel may be selectively masked via the Interrupt
Status Mask register of that channel. Pending interrupts will
cause the INT line to be activated and will be reported via
ISTA (and VISR) only when the mask bits in ISM (and VISM)
have been reset.
Processing
After being initialized via the configuration/mode registers
listed in table 8 and table 9 the PT7A6527 is operational.
The control of the data transfer is performed by commands
from the microcontroller written in the Command Register
(CMDR). Events pertaining to the data transfer are reported
via the Interrupt Status Register (ISTA) pointed to by the
Vectored Interrupt Status Register (VISR). Other events
which do not lead to interrupts may be monitored via the
Status Register (STAR) and information about the receive
frames is found in the RFIFO and in the Receive Frame Byte
Counter (RFBC) register.
The powerful FIFO logic, which consists of a 2 x 32 byte
receive and a 2 x 32 byte transmit FIFO per channel, as well
as an intelligent FIFO controller, builds a flexible interface to
the upper protocol layers implemented in the microcontroller.
Receive Frame Processing
Reception of HDLC frames with three or more bytes between
the opening and closing flags is always reported to the
microcontroller if address comparison is not enabled (AC = 0).
If address comparison is enabled, the reception of the frame is
dependent on the first byte of the received HDLC frame
address field and the selected features of the address compare
function (table 3).
Vector(4Bits)
Int. Status C
INT
Effect
Int. Status D
HDLC controller
Data Sheet
PT7A6527
Ver:4