pt7a6527 Pericom Technology Inc, pt7a6527 Datasheet - Page 10

• Manufacturer Part Number: pt7a6527
• Description: Hdlc Controller
• Manufacturer: Pericom Technology Inc

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Figure 5 Operating Modes of the PT7A6527 (Continued)
Quad Connection Time-Slot Mode
Channel selection is performed via the Time-Slot Select
Registers (TSR). For each HDLC channel, the 8-bit TSR
register gives the position of a time slot with a two-bit
resolution. The length of the time slot, either 1, 2, 7 or 8 bits,
can be selected using the MODE register (CCS1, 0). These
parameters are common to the receive and the transmit
channel.
In the case where the number of bits in a PCM frame is 256 or
512, the frame synchronization signal FSC need not be
provided at every PCM frame beginning, since bit counters
are automatically reset at frame end. When the PCM frame
length is not equal to either 256 or 512 bits, the frame
synchronization signal has to be provided at the beginning of
every PCM frame.
The tristate control output line TSC marks the time slot when
data is transmitted/received by the HDLC controller B.
The position of a time slot with respect to FSC, as a function
of the TSR register contents, is shown in figure 6.
Quad Connection Common Control Mode
PT0080(02/09)
f) Single Connection IOM Mode
e) Single Connection TS Mode
Receive
Transmit
Receive
Transmit
B
Programmable Time-Slots
C
IOM
A
D
Master Collision Mode
Master Collision Mode
10
Channel selection is performed by an active high strobe signal
provided through the FSC input. The strobe signal is common
to all four HDLC channels.
The TSC output is active when the FSC strobe is active.See
Figure 7.
Single Connection TS Mode
The time slots selected by the TSR registers all pertain to the
same PCM highway. The programming of a channel proceeds
exactly as explained above.
The tristate control output line TSC marks the time slots when
data is transmitted / received by any of the four controllers.
See Figure 8.
Single Connection IOM - Mode
The IOM is an interface where a frame is composed of n IOM
channels (n = 8 in figure 10). Each IOM channel has a unique
structure. It consists of: two eight-bit bytes, corresponding to
the ISDN B channels, a MONITOR byte, and a control byte of
which the first two bits are allocated to the ISDN D channel.
Figure 9 shows TSC output in Single Connection IOM Mode.
A
B
C
D
A
B
C
D
B
B
Programmable Time-Slots
Programmable Time-Slots
A
A
C
C
HDLC controller
Data Sheet
PT7A6527
D
D
Receive
Transmit
Collision
Data
Receive
Transmit
Collision
Data
Ver:4