pt7a6527 Pericom Technology Inc, pt7a6527 Datasheet - Page 20

• Manufacturer Part Number: pt7a6527
• Description: Hdlc Controller
• Manufacturer: Pericom Technology Inc

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Operational Description
Microprocessor Interface Operation
The PT7A6527 microcontroller interface can be selected to be
either of the
- Motorola type with control signals CS, R/W, DS; address
- Intel non-multiplexed bus type with control signals CS, WR,
- or of the Intel multiplexed address/data bus type with control
Table 6 summaries the uP interface signals.
The ALE input is used to control the interface type as follows
ALE tied to Vcc => (1)
Table 5 ALE Function
Table 6 Microcontroller Interface Signals of the PT7A6527
PT0080(02/09)
bus A0 … 6; data bus AD0 - 7
RD; Address bus A0 … 6; data bus AD0 - 7
signals CS, WR, RD, ALE; address/data bus AD0 - 7
Register Name
Common
registers
Individual
registers
i = A, B, C, D
ALE
Tied to Vcc
Tied to GND
Switching
Interface
Motorola
Intel
Intel
ACR
CCR
VISR
VISM
ISTA
ISM
STAR
CMDR
MODE
RFBC
TSR
Bus Type
non-multiplexed
non-multiplexed
multiplexed
Value after
Hardware
Reset (hex)
00
00
00
00
00
00
52
00
00
00
00
Bus
Meaning
Address comparison disabled.
Single connection TS mode.
Interrupt vector may be read on AD bus bits 0 - 3.
Bits per frame: 256.
Bit rate is equal to clock rate.
Output drivers are of the push-pull type.
No interrupt from any PT7A6527 channel.
All channel interrupts are enabled.
No interrupts from channel i.
All channel i interrupts enabled.
Transmit FIFO is ready to be written. Receive line is idle.
1.3 version
No commands.
Test loop not active.
No collisions will be detected (unconditional transmission).
Inter-frame time fill = idle.
Receiver de-activated.
Channel i disabled (high impedance output).
Channel capacity is 2 bits/time slot.
Zero bytes received.
Time slot 0 selected.
Address
A0-6
A0 - 6
AD0 - 6
20
ALE tied to GND=> (2)
Edge on ALE => (3)
The occurrence of an edge on ALE, either positive or negative,
at any time during the operation immediately selects interface
type (3). A return to one of the other interface types is possible
only if a hardware reset is issued.
Reset
After a hardware reset (pin RES), the configuration/command
register bits are zeroed. No interrupts are active and all outputs
are in a high impedance state. Table 7 sums up the state of the
PT7A6527 immediately after a hardware reset has been
applied.
Data Bus
AD0 - 7
AD0 -7
AD0 - 7
Control Pins
17
CS
CS
CS
HDLC controller
R/W
WR
WR
8
Data Sheet
PT7A6527
DS
RD
RD
7
Ver:4