71m6543h-igtr/f Maxim Integrated Products, Inc., 71m6543h-igtr/f Datasheet - Page 68

• Manufacturer Part Number: 71m6543h-igtr/f
• Description: Energy Meter Ic
• Manufacturer: Maxim Integrated Products, Inc.

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SPI Safe Mode
71M6543F/H Data Sheet
1) An external host reads data from CE locations to obtain metering information. This can be used in
2) A communication link can be established via the SPI interface: By writing into MPU memory locations,
3) An external DSP can access front-end data generated by the ADC. This mode of operation uses the
4) Flash programming by the external host (SPI Flash Mode).
SPI Transactions
A typical SPI transaction is as follows. While SPI_CSZ is high, the port is held in an initialized/reset state.
During this state, SPI_DO is held in high impedance state and all transitions on SPI_CLK and SPI_DI are
ignored. When SPI_CSZ falls, the port begins the transaction on the first rising edge of SPI_CLK. As
shown in
byte, followed by one or more bytes of data. The transaction ends when SPI_CSZ is raised. Some
transactions may consist of a command only.
When SPI_CSZ rises, SPI command bytes that are not of the form x0000000 cause the SPI_CMD (SFR
0xFD) register to be updated and then cause an interrupt to be issued to the MPU. The exception is if the
transaction was a single byte. In this case, the SPI_CMD byte is always updated and the interrupt issued.
SPI_CMD is not cleared when SPI_CSZ is high.
The SPI port supports data transfers up to 10 Mb/s. A serial read or write operation requires at least 8
clocks per byte, guaranteeing SPI access to the RAM is no faster than 1.25 MHz, thus ensuring that SPI
access to DRAM is always possible.
The SPI_STAT byte is output on every SPI transaction and indicates the parity of the previous transaction
and the error status of the previous transaction. Potential error sources are:
68
Command
Address
Status
Name
Field
Data
applications where the 71M6543F/H function as a smart front-end with preprocessing capability. Since
the addresses are in 16-bit format, any type of XRAM data can be accessed: CE, MPU, I/O RAM, but
not SFRs or the 80515-internal register bank.
the external host can initiate and control processes in the 71M6543F/H MPU. Writing to a CE or
MPU location normally generates an interrupt, a function that can be used to signal to the MPU that
the byte that had just been written by the external host must be read and processed. Data can also
be inserted by the external host without generating an interrupt.
71M6543F/H as an analog front-end (AFE).
71M6543F/H not ready
Transaction not ending on a byte boundary.
Table
Yes, if transaction
Yes, if transaction
includes DATA
includes DATA
57, a transaction consists of an optional 16 bit address, an 8 bit command, an 8 bit status
Yes, except
transaction
single byte
Required
Yes
© 2008–2011 Teridian Semiconductor Corporation
(bytes)
more
Size
1 or
2
1
1
Table 57: SPI Transaction Fields
Description
16-bit address. The address field is not required if the transaction
is a simple SPI command.
8-bit command. This byte can be used as a command to the
MPU. In multi-byte transactions, the MSB is the R/W bit. Unless
the transaction is multi-byte and SPI_CMD is exactly 0x80 or
0x00, the SPI_CMD register is updated and an SPI interrupt is
issued. Otherwise, the SPI_CMD register is unchanged and the
interrupt is not issued.
8-bit status field, indicating the status of the previous transaction.
This byte is also available in the MPU memory map as
SPI_STAT (I/O RAM 0x2708). See
The read or write data. Address is auto incremented for each
new byte.
Table 59
for the contents.
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