71m6543h-igtr/f Maxim Integrated Products, Inc., 71m6543h-igtr/f Datasheet - Page 112

• Manufacturer Part Number: 71m6543h-igtr/f
• Description: Energy Meter Ic
• Manufacturer: Maxim Integrated Products, Inc.

71M6543F/H Data Sheet
112
Name
PLS_MAXWIDTH[7:0]
PLS_INTERVAL[7:0]
PLS_INV
PORT_E
PRE_E
PREBOOT
RCMD[4:0]
RESET
RFLY_DIS
RMT2_E
RMT4_E
RMT6_E
RMT_RD[15:8]
RMT_RD[7:0]
SFR FC[4:0] 0
SFRB2[7]
Location Rst Wk Dir
210A[7:0] FF FF R/W
210B[7:0]
2602[7:0]
2603[7:0]
210C[0]
270C[5]
210C[3]
2704[5]
2200[3]
2709[3]
2709[4]
2709[5]
0
0
0
0
–
0
0
0
0
0
0
0
0
–
0
0
0
0
0
© 2008–2011 Teridian Semiconductor Corporation
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
Description
PLS_MAXWIDTH[7:0] determines the maximum width of the pulse (low-going pulse if
PLS_INV=0 or high-going pulse if PLS_INV=1). The maximum pulse width is
(2*PLS_MAXWIDTH[7:0] + 1)*T
clock cycles. If PLS_INTERVAL[7:0] = 0 or PLS_MAXWIDTH[7:0] = 255, no pulse
width checking is performed and the output pulses have 50% duty cycle. See
VPULSE and
PLS_INTERVAL[7:0] determines the interval time between pulses. The time between
output pulses is PLS_INTERVAL[7:0]*4 in units of CK_FIR clock cycles. If
PLS_INTERVAL[7:0] = 0, the FIFO is not used and pulses are output as soon as the CE
issues them. PLS_INTERVAL[7:0] is calculated as follows:
PLS_INTERVAL[7:0]
frame / 4 )
For example, since the 71M6543F/H CE code is written to generate 6 pulses in one
integration interval, when the FIFO is enabled (i.e., PLS_INTERVAL[7:0] ≠ 0) and that the
frame duration is 1950 CK_FIR clock cycles, PLS_INTERVAL[7:0] should be written with
Floor(1950 / 6 / 4) = 81 so that the five pulses are evenly spaced in time over the
integration interval and the last pulse is issued just prior to the end of the interval. See
2.3.6.2 VPULSE and
Inverts the polarity of WPULSE and VARPULSE. Normally, these pulses are active low.
When inverted, they become active high. PLS_INV has no effect on XPULSE or
YPULSE.
Enables outputs from the SEGDIO0-SEGDIO15 pins. PORT_E = 0 blocks the momentary
output pulse that occurs when SEGDIO0-SEGDIO15 are reset on power-up.
Enables the 8x pre-amplifier.
Indicates that pre-boot sequence is active.
When the MPU writes a non-zero value to RCMD, the 71M6543F/H issues a command
to the appropriate remote sensor. When the command is complete, the 71M6543F/H
clears RCMD.
When set, writes a one to WF_RSTBIT and then causes a reset.
Controls how the 71M6543F/H drives the power pulse for the 71M6xxx. When set, the
power pulse is driven high and low. When cleared, it is driven high followed by an open
circuit fly-back interval.
Enables the remote interface.
Response from remote read request.
WPULSE.
= Floor ( Mux frame duration in CK_FIR cycles / CE pulse updates per Mux
WPULSE.
I
. Where T
I
is PLS_INTERVAL[7:0] in units of CK_FIR
2.3.6.2
v1.0