sc16c751b NXP Semiconductors, sc16c751b Datasheet - Page 23
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sc16c751b
Manufacturer Part Number
sc16c751b
Description
5 V, 3.3 V And 2.5 V Uart With 64-byte Fifos
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C751B.pdf
(32 pages)
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SC16C751B_2
Product data sheet
Fig 5.
Fig 6.
Applies to external clock, crystal oscillator max 24 MHz.
RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
Reset pulse must happen when these signals are inactive: CS, IOR, IOW.
General read timing
General write timing
D0 to D7
D0 to D7
A0 to A2
A0 to A2
IOR
IOW
CS
CS
10.1 Timing diagrams
t
t
6s'
6s'
t
t
13d
7d
address
address
t
valid
valid
12d
active
active
active
active
t
t
7w
13w
Rev. 02 — 10 October 2008
t
16s
data
data
t
t
t
12h
16h
t
7h'
7h'
t
t
9d
15d
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
t
t
6s'
6s'
address
address
t
12d
valid
valid
active
active
t
t
7w
13w
t
16s
t
t
7h'
7h'
SC16C751B
t
t
12h
16h
© NXP B.V. 2008. All rights reserved.
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