sc16c751b NXP Semiconductors, sc16c751b Datasheet - Page 14

• Manufacturer Part Number: sc16c751b
• Description: 5 V, 3.3 V And 2.5 V Uart With 64-byte Fifos
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC16C751B_2
Product data sheet
7.3.1 FIFO mode
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs and set the receive FIFO trigger
levels.
Table 8.
Table 9.
Bit
7:6
5
4:3
2
1
0
FCR[7]
0
0
1
1
Symbol
FCR[7]
(MSB),
FCR[6] (LSB)
FCR[5]
FCR[4:3]
FCR[2]
FCR[1]
FCR[0]
FIFO Control Register bits description
RCVR trigger levels
FCR[6]
0
1
0
1
Description
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO equals
the programmed trigger level. However, the FIFO will continue to be loaded
until it is full. Refer to
64-byte FIFO enable.
reserved
XMIT FIFO reset.
RCVR FIFO reset.
FIFO enable.
Rev. 02 — 10 October 2008
logic 0 = 16-byte mode (normal default condition)
logic 1 = 64-byte mode
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO
RX FIFO trigger level (bytes)
16-byte operation
1
4
8
14
Table
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
9.
64-byte operation
1
16
32
56
SC16C751B
© NXP B.V. 2008. All rights reserved.
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