sc16c751b NXP Semiconductors, sc16c751b Datasheet - Page 11

• Manufacturer Part Number: sc16c751b
• Description: 5 V, 3.3 V And 2.5 V Uart With 64-byte Fifos
• Manufacturer: NXP Semiconductors

NXP Semiconductors
7. Register descriptions
Table 6.
[1]
[2]
[3]
[4]
SC16C751B_2
Product data sheet
A2 A1 A0 Register Default
General register set
0
0
0
0
0
0
1
1
1
1
Special register set
0
0
The value shown represents the register’s initialized hex value; X = n/a.
These registers are accessible only when LCR[7] = 0.
Do not write a logic 1 to the reserved bits. Read of the reserved bits reflect unknown values.
The ‘Special register set’ is accessible only when LCR[7] is set to a logic 1.
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
SC16C751B internal registers
RHR
THR
IER
FCR
ISR
LCR
MCR
LSR
MSR
SPR
DLL
DLM
[4]
[2]
Table 6
assigned bit functions are more fully defined in
XX
XX
00
00
01
00
00
60
X0
FF
XX
XX
details the assigned bit functions for the fifteen SC16C751B internal registers. The
[1]
Bit 7
bit 7
bit 7
0
RCVR
trigger
(MSB)
FIFOs
enabled
divisor
latch
enable
0
FIFO
data
error
reserved reserved reserved CTS
bit 7
bit 7
bit 15
Bit 6
bit 6
bit 6
0
RCVR
trigger
(LSB)
FIFOs
enabled
set break set
0
trans.
empty
bit 6
bit 6
bit 14
Rev. 02 — 10 October 2008
Bit 5
bit 5
bit 5
Low
power
mode
64-byte
FIFO
enable
64-byte
FIFO
enable
parity
flow
control
enable
trans.
holding
empty
bit 5
bit 5
bit 13
Bit 4
bit 4
bit 4
Sleep
mode
reserved
[3]
0
even
parity
loopback
break
interrupt
bit 4
bit 4
bit 12
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
Section 7.1
Bit 3
bit 3
bit 3
modem
status
interrupt
reserved
[3]
INT
priority
bit 2
parity
enable
reserved
[3]
framing
error
reserved reserved reserved
bit 3
bit 3
bit 11
through
Bit 2
bit 2
bit 2
receive
line
status
interrupt
XMIT
FIFO
reset
INT
priority
bit 1
stop bits word
reserved
[3]
parity
error
bit 2
bit 2
bit 10
SC16C751B
Section
Bit 1
bit 1
bit 1
transmit
holding
register
RCVR
FIFO
reset
INT
priority
bit 0
length
bit 1
RTS
overrun
error
bit 1
bit 1
bit 9
© NXP B.V. 2008. All rights reserved.
7.10.
Bit 0
bit 0
bit 0
receive
holding
register
FIFO
enable
INT
status
word
length
bit 0
reserved
[3]
receive
data
ready
bit 0
bit 0
bit 8
CTS
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