xr17c152im Exar Corporation, xr17c152im Datasheet - Page 8

• Manufacturer Part Number: xr17c152im
• Description: 5v Pci Bus Dual Uart
• Manufacturer: Exar Corporation

XR17C152
5V PCI BUS DUAL UART
The PCI local bus configuration space registers are responsible for setting up the device’s operating
environment in the PCI local bus. The pre-defined operating parameters of the device are read by the PCI bus
plug-and-play auto-configuration manager in the operating system. After the PCI bus has collected all data
from every device/card on the bus, it defines and downloads the memory mapping information to each device/
card about their individual operation memory address location and conditions. The operating memory mapped
address location is downloaded into the Base Address Register (BAR) register, 0x10. The plug-and-play auto
configuration feature is only available when an external 93C46 EEPROM is used. The EEPROM contains the
device vendor and sub-vendor data required by the auto-configuration setup.
1.1
A
DDRESS
0x0C
0x00
0x04
0x08
0x10
0x14
PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
15:0
30
29:28
27
26:25
24
23
22:16
15:9,7,
5,4,3,2
8
6
1
0
7:0
31:24
23:16
15:8
7:0
9:0
31:16
31
31:8
31:10
31:0
B
ITS
R-Reset
RWR
RWR
RWC
RWC
RWR
RWR
RWR
RWR
T
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
T
YPE
ABLE
1
1
1: PCI L
Device ID (Exar device ID number or from EEPROM)
Vendor ID (Exar ID or from EEPROM) assigned by PCISIG
Parity error detected. Cleared by writing a logic 1.
System error detected. Cleared by writing a logic 1.
Unused
Target Abort. Set whenever 152 terminates with a target abort.
DEVSEL# timing.
Unimplemented bus master error reporting bit
Fast back to back transactions are supported
Reserved Status bits
Command bits (reserved)
SERR# driver enable. Logic 1=enable driver and 0=disable
driver
Parity error enable. Logic 1=respond to parity error and 0=ignore
Command controls a device’s response to mem space accesses:
0=disable mem space accesses, 1=enable mem space accesses
Command controls a device’s response to I/O space accesses:
0 = disable I/O space accesses 1 = enable I/O space accesses
Class Code (Simple 550 Communication Controller).
Revision ID (Exar device revision number)
BIST (Built-in Self Test)
Header Type (a single function device with one BAR)
Unimplemented Latency Timer (needed only for bus master)
Unimplemented Cache Line Size
Memory Base Address Register (BAR)
Claims a 1K address space for the memory mapped UARTs
Unimplemented Base Address Register (returns zeros)
OCAL
B
US
C
ONFIGURATION
8
D
ESCRIPTION
S
PACE
R
EGISTERS
áç
áç
áç
áç
Current Rev. value
00 0000 0000
R
0x00000000
0x00 00 00
ESET
0x070002
000 0000
0x13A8
0x0152
0x0000
(
0000
0x00
0x00
0x00
0x00
HEX
00
0
0
1
0
0
0
0
REV. 1.2.0
V
ALUE
)