xr17c152im Exar Corporation, xr17c152im Datasheet - Page 21

• Manufacturer Part Number: xr17c152im
• Description: 5v Pci Bus Dual Uart
• Manufacturer: Exar Corporation

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REV. 1.2.0
There are two methods to load transmit data and unload receive data from each UART channel. First, there is
a transmit data register and receive data register for each UART channel in the device configuration register
set to ease programming. These registers support 8, 16, 24 and 32 bits wide format. In the 32-bit format, it
increases the data transfer rate on the PCI bus. Additionally, a special register location provides receive data
byte with its associated error tags. This is a 16-bit or 32-bit read operation where the Line Status Register
(LSR) content in the UART channel register is paired along with the data byte. This operation further facilitates
data unloading with the error tags without having to read the LSR register separately. Furthermore, the
XR17C152 supports PCI burst mode for read/write operation of up to 64 bytes of data.
The second method is through each UART channel’s transmit holding register (THR) and receive holding
register (RHR). The THR and RHR registers are 16550 compatible so their access is limited to 8-bit format.
The software driver must separately read the LSR content for the associated error tags before reading the data
byte.
The XR17C152 supports PCI Burst Read and PCI Burst Write transactions anywhere in the mapped memory
region (except reserved areas). In addition, to utilize this feature fully, the device provides a separate memory
location (apart from the 16550 register set) where the RX and the TX FIFO can be read from/written to, as
shown in
locations:
The RX FIFO data (up to the maximum 64 bytes) can be read out in a single burst 32-bit read operation
(maximum 16 DWORD reads) at memory locations 0x100 (channel 0) and 0x300 (channel 1). This operation is
at least 16 times faster than reading the data in 64 separate 8-bit memory reads of RHR register (0x000 for
channel 0 and 0x200 for channel 1).
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3.0 TRANSMIT AND RECEIVE DATA
3.1
3.1.1
WITH N
Read n+0 to n+3
Read n+4 to n+7
R
EAD
DATA LOADING AND UNLOADING VIA 32-BIT PCI BURST TRANSFERS
Channel 0:
Channel 1:
Etc.
RX FIFO,
O
Table 2 on page
Normal Rx FIFO Data Unloading at locations 0x100 (channel 0) and 0x300 (channel 1)
E
RRORS
RX FIFO
TX FIFO
RX FIFO + status
RX FIFO
TX FIFO
RX FIFO + status
FIFO Data n+3
FIFO Data n+7
10. The following is an extract from the table showing the burstable memory
B
YTE
3
:
:
:
:
:
:
FIFO Data n+2
FIFO Data n+6
0x100 - 0x13F (64 bytes)
0x100 - 0x13F (64 bytes)
0x180 - 0x1FF (64 bytes data + 64 bytes status)
0x300 - 0x33F (64 bytes)
0x300 - 0x33F (64 bytes)
0x380 - 0x3FF (64 bytes data + 64 bytes status)
B
YTE
21
2
FIFO Data n+1
FIFO Data n+5
B
YTE
1
5V PCI BUS DUAL UART
FIFO Data n+0
FIFO Data n+4
B
YTE
XR17C152
0