xr17c152im Exar Corporation, xr17c152im Datasheet - Page 28

• Manufacturer Part Number: xr17c152im
• Description: 5v Pci Bus Dual Uart
• Manufacturer: Exar Corporation

XR17C152
5V PCI BUS DUAL UART
Automatic hardware RTS/CTS or DTR/DSR flow control is used to prevent data overrun to the local receiver
FIFO and remote receiver FIFO. The RTS#/DTR# output pin is used to request the remote unit to suspend/
restart data transmission while the CTS#/DSR# input pin is monitored to suspend/restart the local transmitter.
The auto RTS/CTS or DTR/DSR flow control features are individually selected to fit specific application
requirement and enabled through EFR bit-6 and 7 and MCR bit-2 for either RTS/CTS or DTR/DSR control
signals.
Auto RTS flow control must be started by asserting the RTS# output pin LOW (MCR bit-1 = 1). Similarly, Auto
DTR flow control must be started by asserting the DTR# output pin LOW (MCR bit-0 = 1).
detail how automatic hardware flow control works.
F
4.4
4.3.3
IGURE
MCR B
Receive Data
Byte and Errors
16X or 8X Sampling
Clock (8XMODE Reg.)
13. R
Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation
Receiver Operation with FIFO
X
0
0
1
1
64 bytes by 11-
bit wide FIFO
IT
ECEIVER
-2
T
ABLE
O
PERATION IN
10: A
EFR B
Receive Data Shift
Register (RSR)
UTO
X
X
1
1
0
Receive Data
IT
Receive
(64-byte)
FIFO
-7
FIFO
Data
RTS/CTS
AND
F
Data falls to 40
FIFO Trigger=48
Data fills to 56
Validation
OR
LOW
Data Bit
Example:
- FIFO trigger level set at 48 bytes
- RTS/DTR hyasteresis set at +/-8 chars.
EFR B
DTR/DSR F
C
28
ONTROL
X
X
0
1
1
IT
-6
RTS#/DTR# re-asserts when data falls below the
trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RTS#/DTR# de-asserts when data fills above
the trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RHR Interrupt (ISR bit-2) is programmed at
FIFO trigger level (RXTRG).
FIFO is Enable by FCR bit-0=1
M
LOW
ODE
C
ONTROL
H
ARDWARE
Auto DSR Flow Control Enabled
Auto DTR Flow Control Enabled
Auto CTS Flow Control Enabled
Auto RTS Flow Control Enabled
No Hardware Flow Control
S
Receive Data Characters
ELECTION
F
LOW
C
ONTROL
Figure 14
áç
áç
áç
áç
S
RXFIFO1
ELECTION
REV. 1.2.0
shows in